I/O Library IP
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I/O Library IP
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Bi-Directional LVDS with LVCMOS
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
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MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
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MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- Combo PHY for both MIPI D-PHY CSI-2 RX and LVDS
- TSMC 28HPC+
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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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1.8V general purpose I/O for 4nm FinFET
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
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3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
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Four Channel (4CH) LVDS in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 175 Mbps - 1000 Mbps bandwidth/channel
- Up to 4 Gbps data throughput
- 7-bit/10-bit serial data transmitted per pixel clock per channel
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Four Channel (4CH) LVDS Receiver in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- Consists of 1 Clock lane and up to 4 Data lanes
- Up to 1.0 Gbps bandwidth per channel
- Up to 4.0 Gbps data throughput
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MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
- 80 Mbps to 1.2 Gbps data rate per lane in high-speed D-PHY mode
