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I/O Library IP

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Compare 1,225 I/O Library IP from 51 vendors (1 - 10)
  • 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
    • The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.
    • Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.
    Block Diagram -- 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
  • 3.3V Capable GPIO on TSMC 28nm RF HPC+
    • The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 3.3V Capable GPIO on TSMC 28nm RF HPC+
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
  • Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
    • A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
    • This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic.
    Block Diagram -- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
  • LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
    • KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF.
    • The differential voltage swing can be programmable from 0.35V to 1V.
    • The output enable control function can be activated to decide the IO as input/output function. This IP also includes the IO PAD.
    Block Diagram -- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
  • LVDS and OpenLDI PHY
    • Silicon proven with maximum speed @1.5Gbps per lane
    • Suitable for Automotive applications with ESD levels: HBM > 4KV and CDM > 750V
    • LVDS TX PHY: 4-data lanes plus 1-clock lane with each lane can be individually turned off
    • Supports long-distance transmission: Capable of maintaining signal integrity over longer cable length
    Block Diagram -- LVDS and OpenLDI PHY
  • SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
    • The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • LVDS Serializer IP
    • The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
    • The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Serializer IP
  • MIPI D-PHY/LVDS Combo Receiver IP
    • The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
    • The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).
    Block Diagram -- MIPI D-PHY/LVDS Combo Receiver IP
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