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UCIe IP

UCIe IP Cores (Universal Chiplet Interconnect Express) facilitate high-bandwidth communication between heterogeneous chiplets, in a single package.

The UCIe™ physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe™ controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe™ architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.

Explore our vast directory of UCIe IP Cores below.

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Compare 50 UCIe IP from 16 vendors (1 - 10)
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • Universal Chiplet Interconnect Express(UCIe) VIP
    • The UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs
    • The UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols
    • The UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters
    Block Diagram -- Universal Chiplet Interconnect Express(UCIe) VIP
  • The UCIe CONTROLLER IP
    • The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and advanced mainband links and sideband links
    Block Diagram -- The UCIe CONTROLLER IP
  • UCLe - Ensures reliable validation and efficient connectivity for chiplets
    • UCIe VIP is a state-of-the-art solution for validating and ensuring compliance in multi-chip semiconductor systems. With features like high-speed data transfer, protocol compliance, and advanced debugging, it guarantees robust and efficient chiplet communication.
    • This technology powers diverse applications, including HPC, AI/ML, automotive electronics, and telecommunications. It ensures seamless data flow, reliability, and energy efficiency across industries like edge computing, cloud platforms, and consumer electronics
    Block Diagram -- UCLe - Ensures reliable validation and efficient connectivity for chiplets
  • UCIe D2D Adapter
    • The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer.
    • By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits.
    Block Diagram -- UCIe D2D Adapter
  • Simulation VIP for UCIE
    • Protocol Layer Features
    • Streaming mode
    • PCIe mode
    • Protocol FDI LSMs
    Block Diagram -- Simulation VIP for UCIE
  • UCIe Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe Verification IP
  • UCIe 2.0 Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe 2.0 Verification IP
  • Universal Chiplet Interconnect Express (UCIe™) PHY
    • Supports up to 32Gbps per pin including 4/8/12/16/24Gbps
    • Forwarded clock, track, and valid pins
    • Sideband messaging for link training and parameter exchange
    • KGD (Known Good Die) testing capability
    • Redundant lane repair (advanced)
    • Width degradation (standard)
    • Lane reversal
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe™) PHY
  • Universal Chiplet Interconnect Express (UCIe™) Controller
    • Lowest latency controller for data intensive die-to-die applications
    • Supports single and multiple PHY modules
    • CXS, CHI C2C, AXI, PCIe, CXL, and streaming protocols
    • CRC and retry mechanism
    • Sideband messaging for link training, parameter exchange, and vendor defined messages
    • Link State Management
    • Parameter Negotiation
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe™) Controller
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