UCIe IP
UCIe IP Cores (Universal Chiplet Interconnect Express) facilitate high-bandwidth communication between heterogeneous chiplets, in a single package.
The UCIe™ physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe™ controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe™ architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.
Explore our vast directory of UCIe IP Cores below.
All offers in
UCIe IP
Filter
Compare
54
UCIe IP
from
18
vendors
(1
-
10)
-
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- Low latency controller for UCIe-based multi-die designs
- Includes Die-to-Die Adapter layer and Protocol layer
-
UCIe Controller add-on CXL3 Protocol Layer
- UCIe Controller add-on CXL3 Protocol Layer
-
UCIe Controller add-on CXL2 Protocol Layer
- UCIe Controller add-on CXL2 Protocol Layer
-
UCIe Controller baseline for Streaming Protocols
- Low latency controller for UCIe-based multi-die designs
- Includes Die-to-Die Adapter layer and Protocol layer
- Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
- Error detection and correction with optional CRC and retry functionality
-
UCIe 2.0 Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support.
-
UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support.
-
Verification IP for UCIe
- Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics.
- PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.
-
UCIe Die-to-Die Controller IP
- GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UCIe 2.0 specification and supporting UCIe Streaming protocol applications.
- With the AresCORE D2D PHY IP, GammaCORE provides the complete UCIe solution for an open and robust chiplet ecosystem.
-
UCIe Die-to-Die PHY
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
-
Die-to-Die PHY
- The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and are available on both standard and advanced packaging.
