IP Catalog > Network-on-Chip (NoC) IP

Network-on-Chip (NoC) IP

Networks-on-Chip (NoC) are advanced communication architectures designed to facilitate efficient data transfer within complex Systems-on-Chip (SoCs). By connecting multiple cores, memory modules, and other components, NoC technology provides scalable, high-performance solutions that improve bandwidth, reduce latency, and optimize power consumption. Ideal for applications in high-performance computing, AI, IoT, and mobile devices, Networks-on-Chip ensure seamless communication in modern multi-core systems.

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Compare 19 Network-on-Chip (NoC) IP from 10 vendors (1 - 10)
  • High speed NoC (Network On-Chip) Interconnect IP
    • The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow.
    • It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.
    Block Diagram -- High speed NoC (Network On-Chip) Interconnect IP
  • Scalable Switch Fabric
    • The NeuraScale Scalable Switch Fabric is a WeaveIP™ advanced system IP solution that is designed from the ground-up to provide non-blocking switching between a large number of UALink™, Ultra Ethernet, or AMBA ports for the emerging scale-up and scale-out systems. ​
    • Extreme port density is achieved while maintaining near lowest theoretical latency, tight latency-bandwidth curve and simple physical design with design tiles. 
    Block Diagram -- Scalable Switch Fabric
  • Smart Network-on-Chip (NoC) IP
    • Smart NoC automation
    • Topology generation with minimum wire length
    • Scripting-driven regular topology creation
    • Incremental design capability
    • Auto-timing closure assist
    Block Diagram -- Smart Network-on-Chip (NoC) IP
  • FlexNoC 5 Interconnect IP
    • Physical Awareness for faster timing closure
    • Higher margins
    • Fewer wires
    Block Diagram -- FlexNoC 5 Interconnect IP
  • NoC System IP
    • Packetization allows a reduction of the wire count
    • Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
    • Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster
    Block Diagram -- NoC System IP
  • FlexNoC 5 Option For Scalability and Performance Critical Systems
    • Scales from 10s to 100s of IP blocks
    • Automatically generates ring, mesh and torus networks
    • View and edit generated topologies
    Block Diagram -- FlexNoC 5 Option For Scalability and Performance Critical Systems
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Tessent Bus Monitor
    • Full transaction and trace-level visibility of on-chip bus traffic
    • Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
    • Supports AXI, ACE, ACE-lite
    • Run-time configurable
    Block Diagram -- Tessent Bus Monitor
  • Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
    • Drag & Drop Graphical User Interface
    • Unified configuration tree view
    • Intelligent routing path calculation
    Block Diagram -- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
  • FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
    • ARM® Cortex®-R5 and Cortex-R7 processor port checking
    • Hardware duplication and redundancy
    • Custom ECC and parity generation and checking
    Block Diagram -- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
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