Network-on-Chip (NoC) IP

Networks-on-Chip (NoC) are advanced communication architectures designed to facilitate efficient data transfer within complex Systems-on-Chip (SoCs). By connecting multiple cores, memory modules, and other components, NoC technology provides scalable, high-performance solutions that improve bandwidth, reduce latency, and optimize power consumption. Ideal for applications in high-performance computing, AI, IoT, and mobile devices, Networks-on-Chip ensure seamless communication in modern multi-core systems.

All offers in Network-on-Chip (NoC) IP

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Compare 23 Network-on-Chip (NoC) IP from 13 vendors (1 - 10)

High-scalable, high-performance Interconnect fabric IP with cache coherence support
- High bandwidth, low power consumption, low latency
- Support Component Aggregation Layer (CAL)
- Topology: Mesh
- Support multiple I/O Coherent Master Nodes (CIO)
- Maximum node count: 12x12
Interconnect fabric IP with cache coherence support
- StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC.
High speed NoC (Network On-Chip) Interconnect IP
- The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow.
- It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.
Scalable Switch Fabric
- The NeuraScale Scalable Switch Fabric is a WeaveIP™ advanced system IP solution that is designed from the ground-up to provide non-blocking switching between a large number of UALink™, Ultra Ethernet, or AMBA ports for the emerging scale-up and scale-out systems.
- Extreme port density is achieved while maintaining near lowest theoretical latency, tight latency-bandwidth curve and simple physical design with design tiles.
Smart Network-on-Chip (NoC) IP
- Smart NoC automation
- Topology generation with minimum wire length
- Scripting-driven regular topology creation
- Incremental design capability
- Auto-timing closure assist
FlexNoC 5 Interconnect IP
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
NoC System IP
- Packetization allows a reduction of the wire count
- Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
- Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster
FlexNoC 5 Option For Scalability and Performance Critical Systems
- Scales from 10s to 100s of IP blocks
- Automatically generates ring, mesh and torus networks
- View and edit generated topologies
FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- ARM® Cortex®-R5 and Cortex-R7 processor port checking
- Hardware duplication and redundancy
- Custom ECC and parity generation and checking
Ncore 3 Coherent Network-on-Chip (NoC)
- Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
- AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
- Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
- Configurable last-level caches