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IEEE1588 IP

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Search (27)
Compare 27 IEEE1588 IP from 14 vendors (1 - 10)
  • Multi-Channel Streaming DMA Controller
    • The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
    • The core interfaces with the host memory via a manager AMBA® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.
    Block Diagram -- Multi-Channel Streaming DMA Controller
  • AXI4 to/from AXI4-Stream DMA
    • The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AXI4 bus.
    • The core implements two independent paths: One transfers data from the read manager memory-mapped interface to the manager stream (MM2S) interface.
    Block Diagram -- AXI4 to/from AXI4-Stream DMA
  • AXI4 to/from AXI4-Stream Scatter-Gather DMA
    • The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
    • The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
    Block Diagram -- AXI4 to/from AXI4-Stream Scatter-Gather DMA
  • Stream Direct Memory Access (SDMA)
    • The multi-channel Stream Direct Memory Access (SDMA) controller IP core provides high bandwidth direct memory access between memory and any IP peripherals with an AXI4-Stream interface for up to 16 channels.
    • The SDMA IP utilities a dedicated Write and Read circular buffer structure for data and descriptor(s) for each DMA channel, which helps in offloading data movement tasks from the Central Processing Unit (CPU) in processor-based systems.
    Block Diagram -- Stream Direct Memory Access (SDMA)
  • High Channel Count DMA IP Core for PCI-Express
    • The High Channel Count (HCC) DMA IP core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces.
    • This IP addresses continuous streaming applications from up to 64 different data sources. Each channel is able to transmit data into a separate memory area.
    • Up to 16 AXI Stream masters read DMA Data from the host and present it to the user logic. Additional 8 AXI4 masters are available to interface full AXI or AXI-Lite peripherals with the host.
    Block Diagram -- High Channel Count DMA IP Core for PCI-Express
  • AXI Bridge with DMA for PCIe IP Core
    • The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
    • AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.
    Block Diagram -- AXI Bridge with DMA for PCIe IP Core
  • Multi-Channel AXI DMA Engine
    • The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
    • These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.
    Block Diagram -- Multi-Channel AXI DMA Engine
  • ULL PCIe DMA Controller
    • The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
    • With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.
    Block Diagram -- ULL PCIe DMA Controller
  • AMBA AHB 4 Channel DMA Controller
    • The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
    • The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
    • The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
    Block Diagram -- AMBA AHB 4 Channel DMA Controller
  • AHB Single Channel DMA Controller
    • The AHB Single Channel DMA Controller core is a configurable single channel direct memory access controller.
    • The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
    • The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
    Block Diagram -- AHB Single Channel DMA Controller
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