IP Catalog > Multimedia IP

Multimedia IP

Multimedia IP cores are IP blocks used in the design of multimedia processing systems. These IP cores are typically developed to perform specific functions related to handling multimedia data, such as audio, video, graphics, and imaging. Multimedia IP cores can handle a variety of tasks, including:

  • Video Encoding/Decoding (Codec): IP cores that can compress or decompress video streams (e.g., H.264, HEVC, VP9).
  • Audio Encoding/Decoding: IP cores used to compress or decompress audio data (e.g., MP3, AAC).
  • Image Processing: IP cores for tasks like scaling, filtering, or converting images (e.g., resizing, color space conversion).
  • Graphics Processing: IP cores for rendering graphics, handling 2D or 3D graphics rendering, and processing graphic objects in video games, GUIs, or other visual applications.
  • Video Streaming: IP cores that manage real-time streaming of video data for playback or transmission.
  • Signal Processing: IP cores that process signals from sensors, cameras, microphones, etc., typically to filter, enhance, or interpret the data.
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Search (594)
Compare 594 Multimedia IP from 85 vendors (1 - 10)
  • Image Signal Processing Pipeline IP core
    • Extremely flexible and versatile, ISPIDO can be tailored on ultra low powered battery operated devices, up to higher than 8K resolution vision systems.
    • Each module of the image Signal Processing Pipeline, proposed by DPControl, has been implemented respecting the compatibility with the AMBA AXI4 standards, making the entire architecture completely configurable and versatile.
    • The ISP accepts in input a video stream with 8 or 10 or 12 bits depth. The Defective Correction module takes care of eliminating the Salt-Pepper error.
    Block Diagram -- Image Signal Processing Pipeline IP core
  • LZ4/Snappy Data Compressor
    • LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compression standards.
    • The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers.
    Block Diagram -- LZ4/Snappy Data Compressor
  • Warping Engine IP Core
    • TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory.
    • Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.
    • The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
    Block Diagram -- Warping Engine IP Core
  • OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
    • D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores.
    • It is the first IP to bring 3D graphics OpenGL ES 2.0 rendering (with some ES 3.0 / 3.1 extensions) to the FPGA and SoC world and – with offline-shader compilers – even into MCUs or low-end MPUs with small amounts of memory and bare-metal or RTOS operation systems.
    Block Diagram -- OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
  • 3D OpenGL ES 1.1 GPU IP core
    • D/AVE 3D is cost-efficient IP core for 3D graphics applications.
    • This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software.
    Block Diagram -- 3D OpenGL ES 1.1 GPU IP core
  • 2.5D GPU
    • The D/AVE HD 2.5D GPU family is an evolution of the D/AVE 2D family supporting high quality 2D and 3D rendering for displays up to 4K x 4K.
    • Targeting modern graphics applications on high resolution displays in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets, the D/AVE HD fixed-function 2.5D GPU core is designed to be fast with powerful functionality.
    Block Diagram -- 2.5D GPU
  • 2D GPU Hardware IP Core
    • D/AVE 2D is a 2D GPU Hardware IP Core, optimized for easy integration into FPGAs and ASICs.
    • Focus of D/AVE 2D is to provide cost efficient high quality vector graphics with subpixel processing and an extended anti-aliasing functionality.
    Block Diagram -- 2D GPU Hardware IP Core
  • 3-D Audio Processing Core
    • The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio virtualization processing in a single design.
    • The 3-D processing allows users to enjoy benefits of a multi-channel sound source with only two reporduction channels. 
    Block Diagram -- 3-D Audio Processing Core
  • Dolby Digital/AC-3/MPEG Audio Decoding Core
    • The J1 is a core cell design of an application specific signal processor which performs both Dolby Digital/AC-3 and MPEG audio decompression in a single design.
    • The J1 is capable of decoding all AC-3 bitstreams with full support for bitstreams encoded with 5.1 channels and data rates of up to 640kb/s.
    • The J1 downmixing capability produces stereo output in either normal or Pro-Logic compatible modes, making it ideal for DVD and set-top applications.
    Block Diagram -- Dolby Digital/AC-3/MPEG Audio Decoding Core
  • H.264 Decoder
    • Thes H.264 Decoder IP Core offers a high-efficiency video decoding solution tailored for a wide range of applications, including multimedia, surveillance, broadcast, and automotive systems.
    • Compliant with the ITU-T H.264/AVC standard, it enables real-time decoding of high-definition video streams while maintaining low latency and power consumption.
    Block Diagram -- H.264 Decoder
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