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Ethernet IP

Ethernet IP cores, including 112G and 224G PHYs, up to 1.6T controllers, MACsec security modules, and Verification IP, offer optimized power, performance, area, and latency for automotive, HPC, AI, and IoT SoCs.

Ethernet is defined in a number of IEEE 802.3 standards. These standards define the physical and data-link layer specifications for Ethernet.

Explore our vast directory of Ethernet IP cores below

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Search (389)
Compare 389 Ethernet IP from 68 vendors (1 - 10)
  • Centralised Network Configurator
    • Centralized Network Configurator or CNC is a component used in Time Sensitive Networking (TSN) networks.
    • The CNC monitors data streams while coordinating and managing network configuration.
    • The CNC is based on the stream reservation protocol (802.1 Qcc) to optimize the efficient use of network resources and provide Quality of Service (QoS).
    Block Diagram -- Centralised Network Configurator
  • Block Diagram -- Bridge
  • Zonal Controller
    • Complete solution that integrates both hardware and software components including a TSN-capable Ethernet switch, a Root of Trust security module, and a transport protocol encapsulation system based on IEEE 1722
    Block Diagram -- Zonal Controller
  • Ethernet Controller
    • The Ethernet Controller is an ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connectivity across a broad range of embedded and enterprise applications.
    • Comcores offers controllers ranging from 10M to 800G enabling seamless integration into systems requiring Ethernet connectivity.
    Block Diagram -- Ethernet Controller
  • 10M/100M/1G/2.5G Ethernet TSN End Station Controller IP
    • The 10M/100M/1G/2.5G Ethernet TSN Endstation Controller IP is a comprehensive hardware and software solution for automotive, aerospace and industrial applications. 
    •  The solution implements Timing & Synchronization (802.1AS), Multiple types of Traffic Shaping (802.1Qav, 802.1Qby, 802.1Qcr), Frame preemption (802.1Qbu), Frame replication & elimination (802.1CB), Steam filtering & policing (802.1Qci), and optional MACsec encryption/decryption (802.1AE).
    Block Diagram -- 10M/100M/1G/2.5G Ethernet TSN End Station Controller IP
  • 10M End Station Controller
    • The 10M End Station Controller IP is a comprehensive hardware and software solution. It contains a Media Access Controller (MAC), a Time Of Day (TOD) system and an optional MACsec protection block.
    • The solution can interface with nearly any microcontroller or embedded processor system, either via SPI or AXI Memory Mapped host interface. The host interface can simultaneously transfer both transmit and receive packets, and the End Station Controller supports store and forward or cut-through packet handling.
    Block Diagram -- 10M End Station Controller
  • Quad Serial Gigabit Media Independent Interface (QSGMII)
    • QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps.
    • It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
    Block Diagram -- Quad Serial Gigabit Media Independent Interface (QSGMII)
  • Universal Serial 10GE Media Independent Interface (USXGMII)
    • The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
    • Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
    Block Diagram -- Universal Serial 10GE Media Independent Interface (USXGMII)
  • Serial Gigabit Media Independent Interface (SGMII)
    • SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MAC (Media Access Controller) to a PHY (Physical Layer Device).
    • It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
    Block Diagram -- Serial Gigabit Media Independent Interface (SGMII)
  • Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
    •  A combined silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018 and CPRI Specification V7.0 based solution
    • The IP-core supports 1G, 2.5G, 5G, 10G, and 25G Ethernet data rates as well as CPRI data rate option 1 (614.14M) to option 10 (24.33024G).
    Block Diagram -- Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
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