Ethernet IP

Ethernet IP cores, including 112G and 224G PHYs, up to 1.6T controllers, MACsec security modules, and Verification IP, offer optimized power, performance, area, and latency for automotive, HPC, AI, and IoT SoCs.

Ethernet is defined in a number of IEEE 802.3 standards. These standards define the physical and data-link layer specifications for Ethernet.

Explore our vast directory of Ethernet IP cores below

All offers in Ethernet IP
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Compare 371 Ethernet IP from 64 vendors (1 - 10)
  • Ethernet 10/100 PHY
    • Supports MII.
    • Auto-MDX
    • 10/100Mbs operation supported
    • Full/half duplex operation
    Block Diagram -- Ethernet 10/100 PHY
  • 1G/40G/100G/200G/800G Ethernet Controller - Enables accurate validation of Ethernet protocols across speeds
    • XtremeSilica’s Ethernet Controllers support 1G to 800G speeds, ensuring accurate simulation and validation of Ethernet protocols for high-speed networks. With IEEE compliance, advanced features like QoS, VLAN, and error injection, they optimize performance for Ethernet-based SoC designs.
    • These controllers excel in diverse applications, including data centers, telecommunications, cloud computing, HPC, automotive Ethernet, and industrial automation. They provide seamless integration, high throughput, low latency, and robust networking for modern systems across industries.
    Block Diagram -- 1G/40G/100G/200G/800G Ethernet Controller - Enables accurate validation of Ethernet protocols across speeds
  • 100BASE-T1 Verification IP
    • Supports 100BASE-T1 as per 802.3.bw
    • Supports 4b/3b encoding
    • Supports scrambler
    • Supports 3b2T symbol mapping
    Block Diagram -- 100BASE-T1 Verification IP
  • 10BASE-T1S Verification IP
    • Supports 10BASE-T1S as per specification IEEE 802.3cg-2019
    • Supports MII
    • Supports Self-synchronizing Scrambler/Descrambler
    • Supports 4b/5b Encoding/Decoding
    Block Diagram -- 10BASE-T1S Verification IP
  • 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP
    • Follows 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T specification as defined in IEEE 802.3cb
    • Supports scrambler
    • Supports backplane auto-negotation
    • Supports CDR for serial protocols
    Block Diagram -- 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP
  • Gigabit Ethernet Media Access Controller
    • Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
    • The controller provides half- or full-duplex operation, supports jumbo frames, and optionally provides a useful set of statistics counters enabling station management.
    • Furthermore, the core can optionally be configured with a hardware timestamping unit enabling support for the IEEE 1588 precision time protocol (PTP).
    Block Diagram -- Gigabit Ethernet Media Access Controller
  • TSN Ethernet Endpoint Controller
    • The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards.
    • It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.
    Block Diagram -- TSN Ethernet Endpoint Controller
  • Low-Latency 10/100/1000 Ethernet MAC
    • The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
    • Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.  
    Block Diagram -- Low-Latency 10/100/1000 Ethernet MAC
  • TSN Ethernet Switched Endpoint Controller
    • The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-working (TSN) Ethernet networks.
    • It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.
    Block Diagram -- TSN Ethernet Switched Endpoint Controller
  • Multiport TSN Ethernet Switch
    • The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch.
    • It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br).
    Block Diagram -- Multiport TSN Ethernet Switch
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