Building Blocks IP
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RF Power Amplifier Precorrection System
- DPSYS is a complete Digital Precorrection (Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier.
- The system is capable of adjusting both the gain and phase of a complex input signal.
- This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LUT. Complex inputs are sampled on the rising edge of clk when en is high.
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Direct Digital Synthesizer / Periodic waveform generator
- The DDS IP Core is a high-precision Direct Digital Synthesizer2 used for the generation of periodic waveforms.
- On each rising-edge of the sample clock and when the clock-enable is high, the phase in the phase accumulator is incremented by the value phase_inc.
- This phase is quantized to 16-bits and passed as an address to a look-up table which converts the phase into a waveform.
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IIR Filter Second-Order-Section
- 2nd order IIR filter sometimes referred to as a 'bi-quad'.
- Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering.
- The SOS block is modular allowing any number of SOS blocks to be joined in series to implement higher order IIR filters.
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Generic high-speed FIR Filter with symmetry
- FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps.
- Features configurable coefficients and data width. Design uses only half the number of multipliers compared to a normal FIR implementation.
- Matlab®, FDAtool and Simulink® compatible.
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Generic ultra-speed FIR Filter
- FIR filter designed for very high sample rate applications up to 600 MHz.
- Organized as a systolic array, the filter is modular and scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Matlab®, FDAtool and Simulink® compatible.
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Synchronous FIFO with configurable flags and counts
- The sFIFO controls are designed to operate over a wide range of clock frequencies.
- The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
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32-512 Point Streaming FFT Core
- Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
- Inputs and outputs data in the natural order
- Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
- Parameterized bit width.
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128-Point FFT/IFFT IP Core
- The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
- FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.
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ASIP-1 FFT Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions.
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ASIP-2 Programmable Filter Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions
- The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
