Building Blocks IP

Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
Inputs and outputs data in the natural order
Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
Parameterized bit width.

The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.

Platform to design Application Specific Instruction Set Processors (ASIPs).
Ideal for supporting multi-standard systems.
Supports a wide range of complex DSP functions
The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.

Includes QR Decomposition, Dynamic scale and K-best Decoder
Fixed Depth K-Best Decoder (K=16)
Achieves close-to ML BER performance
Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
Supports square and non-square QAM

Fixed Complexity Sphere Decoder providing fixed throughput
Achieves close-to ML BER performance
MATLAB and C model for – MIMO 2×2 and 4×4 – Can be modified to support other MIMO sizes – BPSK, 4-QAM, 16-QAM and 64-QAM
Efficient and optimized FPGA Architecture (4×4 MIMO, 16-QAM)

So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests.
Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.

The FFT is factored into Radix-4 Butterfly operations. When an odd power of two is required, a small radix-2 “follower” stage performs the final iteration. The radix-2 stage does not require a full complex rotator so its cost is minimal.
The Radix-4 Engine fetches one complex word of data each clock cycle. Four interleaved data words are collected then applied to the t0-t3 inputs. On successive clock cycles the engine calculates the four frequency domain outputs f0-f3. These are then stored back into the Working Buffer.

This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
The simple, fully synchronous design allows for fast operation while maintaining a low gate count.
It offers high performance and many features to meet your multimedia, digital video and digital printing applications

The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon® streaming (Avalon-ST) interface
CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation
They also construct narrow-band signals from processed baseband signals using interpolation.