Analog IP
Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.
Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).
Explore our vast directory of Analog IP cores below.
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General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
- Division coefficients of the embedded input and feedback dividers can be set to any integer between 1 and 64 or may be bypassed to save power.
- Higher order dividers and/or pre-scalers are optional.
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32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
- This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
- Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
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32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
- PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
- Full rate CMOS differential input data, centered with half-rate CMOS differential clock
- Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
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All Digital Fractional-N PLL for Performance Computing in UMC 40LP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
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Power-OK Monitor
- The agilePOK is a Power OK monitor that consists of a voltage reference and comparators to set a programmable high and low threshold level for power supply integrity detection.
- The number of trigger outputs can be customized and each threshold can be adjusted during operation to support DVFS operation.
- This monitor can be used to detect loss of power or attacks to the power supply.
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50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- 055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
- It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency.
- LO output signal is CMOS compatible.
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.
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802.15.4G RF Transceiver
- The RF Transceiver (B130RF15P4G) is a dual band (sub-1GHz and 2.4GHz band) integrated transceiver specially designed for smart metering and IEEE 802.15.4g related applications.
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12-bit/16-bit SAR ADC
- 12 bits 100Msps SAR ADC on 28nm process;
- 12 bits 25Msps SAR ADC and Pipeline ADC above 100Msps on 40/55nm process;
- 16 bits 2/1Msps SAR ADC on 40/55nm process;
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106dB, 24-bit audio three-channels ADC in TSMC 40uLP
- tADC106-SW1-LR.01_TSMC_40_uLP is a mixed (analog and digital) Virtual Component (ViC) in TSMC 40uLP containing a three-channel ADC and additional functions offering an ideal mixed signal front end for low power and high quality audio applications.
