IP Catalog > Analog IP

Analog IP

Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.

Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).

Explore our vast directory of Analog IP cores below.

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Search (5,733)
Compare 5,733 Analog IP from 112 vendors (1 - 10)
  • 39GHz High-Efficiency CMOS Power Amplifier for 5G mmWave Applications
    • 2-stage PAEmax = 45%
    • PA-stage DEmax = 54%
    • Psat = 18.3dBm
    • Gain = 19dB
    • Efficiency maintained at lower supply voltages for added reliability
    Block Diagram -- 39GHz High-Efficiency CMOS Power Amplifier for 5G mmWave Applications
  • 28GHz High-Efficiency CMOS Power Amplifier for 5G mmWave Applications
    • 2-stage PAEmax = 52.3%
    • PA-stage DEmax = 61.5%
    • Psat = 19.02dBm
    Block Diagram -- 28GHz High-Efficiency CMOS Power Amplifier for 5G mmWave Applications
  • -40°C to +85°C Low power temperature sensor
    • The 180SMIC_TS_03 is a unique stand-alone solution intended to continuously monitor IC status.
    • Temperature detector consists of temperature sensor unit (the voltage at which is directly proportional to the temperature), analog core, SAR controller as calculation center for temperature measurements, as well as an internal voltage regulator, with an output level of 1.25V.
    Block Diagram -- -40°C to +85°C Low power temperature sensor
  • Temperature sensor
    • SMIC CMOS 0.18 um
    • Output voltage 1.2 V
    • Temperature-compensated voltage in a wide temperature range
    • Low current consumption
    Block Diagram -- Temperature sensor
  • 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
    • 180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
    • It consists of the following main sub-blocks: reference oscillator; main PLL loop: Fractional-N PLL and VCO blocks; secondary digital PLL loop: synchronization subsystem; dividers block: clock generation/delivery subsystem; voltage stabilizers.
    • High frequency synthesis is needed for both phase noise performance and ultra-fine frequency tuning step.
    Block Diagram -- 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
  • 10MHz to 50MHz fractional-N PLL synthesizer
    • UMC 22nm ULP technology
    • 1.8V IO power supply
    • Double 0.8/1.0V Core power supply
    • Embedded low noise bias
    Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer
  • 1.22V/1uA Reference voltage and current source
    • 180XFAB_RS_01 consists of a bandgap reference voltage regulator, formed temperature and power supply variations independent voltage and bias, formed reference currents for internal analog blocks based on an external resistor 69.1kΩ.
    • The block starts to operate after power up on 3.3V to 4.2V voltage and en = “1”.
    • The RS is capable to output one reference voltage for analog blocks vbg_out 1.22V without trimming feature.
    Block Diagram -- 1.22V/1uA Reference voltage and current source
  • ULP Clock Generator - GLOBALFOUNDRIES 22FDX
    • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
    • High energy efficiency: Only 5 μW are consumed during operation
    • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
    Block Diagram -- ULP Clock Generator - GLOBALFOUNDRIES 22FDX
  • Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
    • Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all supply voltages and clock signals needed to run highly efficient SoCs in GlobalFoundries® 22FDX®.
    • Running from only one supply voltage and reference clock, the IP generates its own internal supplies and references, and those needed to run the Racyics® ABX® Generator.
    Block Diagram -- Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
  • ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
    • Clock generation based on a Digitally Controlled Oscillator (DCO)
    • 800 MHz < = DCO frequency < = 2400 MHz
    • Programmable clock frequency dividers for ADPLL loop and clock outputs
    • lock-in < 25 us
    Block Diagram -- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
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