IP Catalog > Analog IP

Analog IP

Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.

Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).

Explore our vast directory of Analog IP cores below.

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Search (5,715)
Compare 5,715 Analog IP from 118 vendors (1 - 10)
  • Temperature Sensor on Samsung 14nm, LN14LPP
    • The temperature sensor indicates the junction temperature as a 12-bit binary digital code.
    • It contains a main sensor, remote probes and an ADC. It is capable of monitoring multiple spots via remote probes.
    • It has a resolution of 0.0625°C /1-code and operates within a junction temperature range of -40°C to 125°C.
    Block Diagram -- Temperature Sensor on Samsung 14nm, LN14LPP
  • Temperature Sensor on Samsung 4nm, LN04LPP
    • The temperature sensor indicates the junction temperature as a 9-bit binary digital code.
    • It contains a main sensor, remote probes and an Analog-to-Digital Converter (ADC).
    • It is possible to monitor multiple spots via remote probes.
    • It has a resolution of 0.5℃/1-code and operates within a junction temperature range of -40℃ to 125℃.
    Block Diagram -- Temperature Sensor on Samsung 4nm, LN04LPP
  • PVT Sensor on Samsung 4nm, LN04LPP
    • The PVT sensor indicates the junction temperature as a 12-bit binary digital code.
    • It contains a main sensor, remote probes and an Analog-to-Digital Converter (ADC).
    • It is possible to monitor multiple spots via remote probes.
    • It has a resolution of 0.0625℃/1-code and operates within a junction temperature range of -40~125℃.
    Block Diagram -- PVT Sensor on Samsung 4nm, LN04LPP
  • Oscillator on Samsung 28nm LNM28FDS
    • OSC2802X is a 1V oscillator with output frequency of 240kHz.
    • It consists of an oscillator (OSC) and a current reference.
    Block Diagram -- Oscillator on Samsung 28nm LNM28FDS
  • Integer PLL on Samsung 8nm LN08LPP
    • PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, and an automatic frequency control (AFC).
    Block Diagram -- Integer PLL on Samsung 8nm LN08LPP
  • Integer PLL on Samsung 28nm LN28FDS
    • PLL2851X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a lock detector and an automatic frequency control (AFC). The maximum output frequency of PLL is 2.5GHz.
    Block Diagram -- Integer PLL on Samsung 28nm LN28FDS
  • Frac-N PLL on Samsung 8nm LN08LPP
    • PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 8nm LN08LPP
  • Frac-N PLL on Samsung 4nm LN04LPP
    • PLLF0434X is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 4nm LN04LPP
  • Frac-N PLL on Samsung 28nm LN28FDS
    • PLL2860X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 28nm LN28FDS
  • Adaptive Body Bias Generator on Samsung 28nm LN28FDS
    • The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.
    • The ABBG is used for either Reverse Body Biasing (RBB) to reduce leakage current of the logic devices or Forward Body Biasing (FBB) to improve the system performance by adjusting the body voltages of transistors.
    Block Diagram -- Adaptive Body Bias Generator on Samsung 28nm LN28FDS
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