Analog IP
Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.
Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).
Explore our vast directory of Analog IP cores below.
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Power-OK Monitor
- The agilePOK is a Power OK monitor that consists of a voltage reference and comparators to set a programmable high and low threshold level for power supply integrity detection.
- The number of trigger outputs can be customized and each threshold can be adjusted during operation to support DVFS operation.
- This monitor can be used to detect loss of power or attacks to the power supply.
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50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- 055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
- It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency.
- LO output signal is CMOS compatible.
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.
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802.15.4G RF Transceiver
- The RF Transceiver (B130RF15P4G) is a dual band (sub-1GHz and 2.4GHz band) integrated transceiver specially designed for smart metering and IEEE 802.15.4g related applications.
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12-bit/16-bit SAR ADC
- 12 bits 100Msps SAR ADC on 28nm process;
- 12 bits 25Msps SAR ADC and Pipeline ADC above 100Msps on 40/55nm process;
- 16 bits 2/1Msps SAR ADC on 40/55nm process;
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106dB, 24-bit audio three-channels ADC in TSMC 40uLP
- tADC106-SW1-LR.01_TSMC_40_uLP is a mixed (analog and digital) Virtual Component (ViC) in TSMC 40uLP containing a three-channel ADC and additional functions offering an ideal mixed signal front end for low power and high quality audio applications.
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Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode
- Ideal regulator for power and voltage islets
- Secured integration in the SoC Embedded RCU (Regulator Control Unit) to manage booting and mode transitions and to ensure data integrity
- Configurable output drive before delivery to fit the application
- Performances in sleep mode: qLR with low quiescent current: 0.2 uA
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Linear Regulator, ultra low quiescent current for retention mode TSMC 40uLPeF
- qLR-Aubrey-ref-1.62-3.63-0.55-2.5.02_TSMC_40_uLPeF is an ultra-low quiescent LDO (Linear regulator) in TSMC 40uLPeF.
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Linear Regulator, ultra low quiescent current for retention mode
- Very low quiescent and leakage for Low-Power
- Retention capability enables optimization of the power consumption depending on the modes and needs of the SoC
- Can supply always-on very low loads
- Low Bill-of-Material: supports external capacitor if required by the system
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Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL
- Can be used to monitor 3.3V battery or voltage regulator output
- Monitored input voltage programmable from 0.55V to 3.3V
- Dual POR and BOR functions
- Low power mode for best consumption in sleep mode
