IP Catalog > Analog IP

Analog IP

Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.

Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).

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Search (5,586)
Compare 5,586 Analog IP from 123 vendors (1 - 10)
  • Video DAC
    • The Video DAC IP is designed for transmitting analog video signals from a video source device to a display device, which can be used to build many analog video interfaces, such as Composite (CVBS, AHD), S-Video (Y/C) and Component (YPrPb, RGB/VGA) video interfaces
    • The Video DAC IP offers reliable implementation of analog video interfaces, which can be integrated in the SoCs used in multimedia devices
    Block Diagram -- Video DAC
  • 10/12-bit SAR ADC
    • The SAR ADC IP is a small-size, low power analog to digital converter which leverages charge-redistribution successive approximation technology
    • It offers a reliable solution of analog-to-digital signal conversion for general application
    • Innosilicon SAR ADC IP consists of input MUX, ADC core, and digital logic
    Block Diagram -- 10/12-bit SAR ADC
  • Process/Voltage/Temperature Sensor
    • The PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations
    • It is a critical component in modern SoC designs, enabling real-time measurement and monitoring of environmental and operational conditions
    • It offers a reliable solution for chip operating condition monitoring applications, such as power supply IR drop measurement, high temperature alert, and dynamic performance adjustment
    Block Diagram -- Process/Voltage/Temperature Sensor
  • Power-On-Reset IP
    • The Power-On-Reset (POR) IP provides reliable reset functions for general applications
    • It is powered by analog supply and monitors both analog and digital supply
    • The POR IP generates a POR signal to reset the digital logic
    Block Diagram -- Power-On-Reset IP
  • PLL
    • The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
    • It can generate a stable high-speed clock from an ultra-wide input clock
    • With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
    Block Diagram -- PLL
  • Master/Slave DLL
    • The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing
    • This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint
    • The DLL PHY is designed to generate precise phase-shifted clocks (e.g
    • 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission
    Block Diagram -- Master/Slave DLL
  • Low Power Audio CODEC/ADC/DAC
    • Innosilicon Audio CODEC IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology
    • The ADC, DAC, PGA, and power amplifier are integrated to provide a complete solution
    • Innosilicon Audio CODEC IP offers reliable solutions for audio signal conversion in high end consumer, automotive, multimedia, and other digital audio systems
    Block Diagram -- Low Power Audio CODEC/ADC/DAC
  • Special Purpose Low (Statistical) offset Operation Amplifier
    • The WEAOPSPLO18PI18RO12M22G is a special purpose low offset buffer for bias generator that provides a buffered ouput for the Temperature Sensor
    • The OpAmp deliberately exhibits systematic offsets to favor near zero Output Voltages
    • It is Ideal for Temperature sensors with Rail – To – Rail Output that can go down to zero values.
    Block Diagram -- Special Purpose Low (Statistical) offset Operation Amplifier
  • Rail to Rail Input and Output Operational Amplifier
    • The WEAOPSP18RI18RO1F22G is a rail to rail input and rail to rail output folded cascode with rail to rail output gm stage with input offset control capability
    • The opamp is ideal for ADC input buffers with offset control requirements for the ADC calibration.
    Block Diagram -- Rail to Rail Input and Output Operational Amplifier
  • Special Purpose Low offset Operational Amplifier
    • The WEAOPSLOSP18NI18RO12M22G is a special purpose low offset buffer for bias generator that provides a buffered output for the bandgap voltage.The OpAmp deliberately exhibits systematic offsets to favor near zero Output Voltages
    • It is Ideal for Power Detector and Temperature sensors with Rail – To – Rail Output that can go down to zero values.
    Block Diagram -- Special Purpose Low offset Operational Amplifier
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