Analog IP
Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.
Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).
Explore our vast directory of Analog IP cores below.
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Analog IP
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Ku-Band Phased Array Tx-FE in TSMC 180nm RF
- The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
- It integrates X+Y transmitter channels on the same die and its low power makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
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Ku-Band Phased Array Rx-FE in TSMC 180nm RF
- The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
- It integrates X+Y receiver channels on the same die and its low noise figure and wide baseband bandwidth makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
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12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
- The TRV101TSM40LP IP is a 1.1V low-power low-silicon-area 12-bit 80MHz Asynchronous-SAR ADC implemented in TSMC Low-Power 40nm CMOS process technology.
- Its 40MHz Nyquist bandwidth makes it especially suitable for use in carrier-aggregated wireless communication integrated circuit subsystems (LTE, WiFi, WiMAX etc).
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Crystal Oscillators
- The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
- These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
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PVT Sensor on INTEL 16
- The PVT Sensor is a highly integrated macro for monitoring process, voltage, and temperature variation on-chip, allowing very high precision even in untrimmed usage.
- It consumes very little power even in operational mode, and leakage power only when measurement is complete.
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4-Phase LC PLL on INTEL 16
- High performance design for meeting low jitter requirements including Ref Clock applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Integrated power supply regulation for low deterministic jitter
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18-40MHz Crystal Oscillator on INTEL-16
- Crystal Oscillator pad macro that supports many industry standard crystals in the 18-40MHz range (e.g. 19.2, 24MHz, 25MHz, 38.4MHz)
- Uses standard CMOS transistors
- Crystal Oscillation Mode: Fundamental
- Power down option for IDDQ testing
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Ultra-low power RF receiver / WakeUp receiver
- Supply current: < 3 uA @ 1.8 V (1 kbit/s)
- Response time: < 30 ms (1 kbit/s)
- Sensitivity: -80 dBm
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Ultra-Low-Power 6-13 Bit 0.5-10 KS/s 10μW Analog-Frontend on XFAB XT018
- The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
- The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s). The preamplifier offers programmable gain from 0.5 to 4. The input voltage range is quasi-rail-to-rail guaranteeing more than +- 1.7 V @ 1.8 V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.
- The overall power consumption of the AFE IP sums up with 10.5 uW at 1 kHz input signal.
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8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
- The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s. The differential output signal of maximum +/- 800 mV is driven onto a load impedance of 100 Ohm and can be calibrated within a range of +/- 25 % of its nominal value to adjust to load conditions.
- The IP needs an external clock with high accuracy and low periodic jitter, because the clock jitter influences the dynamic behavior of the converter.
