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CPRI IP Cores

Welcome to the ultimate CPRI IP hub! Explore our vast directory of CPRI IP cores

The Common Public Radio Interface (CPRI) IP cores implement the CPRI Specification. CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

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Compare 20 CPRI IP Cores from 8 vendors (1 - 10)
  • CPRI verification IP
    • The vendor provides configurable CPRI TX/RX verification IP
    • The CPRI verification IP is fully compatible with CPRI version v7.0 with backward compatibility to previous versions and provides an efficient and effective way to verify the component interfacing with CPRI interface of an IP
    Block Diagram -- CPRI verification IP
  • DiFi IP core
    • The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 targeting ASIC, and FPGA technologies.
    • The DiFi implementation builds on long-time experience designing IP cores for sending and receiving Radio IQ data over Ethernet networks, and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- DiFi IP core
  • CPRI 7.0
    • The Common Public Radio Interface (CPRI) 7.0 core is a silicon agnostic implementation of the CPRI 7.0 specification, which is targeting both ASIC and FPGAs CPRI.
    • CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems.
    • With its extreme flexibility and reduced logic consumption, the CPRI 7.0 IP core is the perfect match whether the application is REC (Radio Equipment Controller) or RE (Radio Equipment).
    Block Diagram -- CPRI 7.0
  • eCPRI
    • eCPRI core is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC or FPGA technologies.
    • The eCPRI implementation builds on Chip Interfaces long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- eCPRI
  • CPRI 6.1
    • Common Public Radio Interface (CPRI) 6.1 core is a silicon agnostic implementation of the CPRI 6.1 specification, which is targeting both ASIC and FPGAs.
    • CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems.
    Block Diagram -- CPRI 6.1
  • eCPRI Verification IP
    • Compliant with eCPRI Specification V2.0.
    • Complete eCPRI Tx/Rx functionality.
    • Supports the eCPRI layer of the eCPRI specification.
    • Supports 5G and enables increased efficiency.
    Block Diagram -- eCPRI Verification IP
  • CPRI Verification IP
    • Compliant with CPRI Specification V4.2/V5.0/V6.0/V6.1/V7.0
    • Complete CPRI Tx/Rx functionality.
    • Supports the Physical link layer (Layer 1) of the CPRI specification.
    • Supports different standard line bit rates of the CPRI specification
    Block Diagram -- CPRI Verification IP
  • CPRI Synthesizable Transactor
    • Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
    • Supports complete CPRI Tx/Rx functionality.
    • Supports the Physical link layer (Layer 1) of the CPRI specification.
    • Supports different standard line bit rates of the CPRI specification
    Block Diagram -- CPRI Synthesizable Transactor
  • eCPRI Controller IIP
    • Compliant with eCPRI Specification v2.1
    • Supports complete eCPRI Tx/Rx Functioanlity
    • Supports various Ethernet Speeds - 10G/25G/40G/100G
    • Supports rich configuration to handle multi mode wireless systems
    Block Diagram -- eCPRI Controller IIP
  • CPRI CONTROLLER IIP
    • Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
    • Complete CPRI Tx/Rx functionality.
    • Supports the Physical link layer (Layer 1) of the CPRI specification.
    • Supports different standard line bit rates of the CPRI specification
    Block Diagram -- CPRI CONTROLLER IIP
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