Memory Controller/PHY IP

Fully compliant with UHSII specification Ver. 4.x
Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
Supports data rates from 390Mbps to 1.56Gbps/ch
RCLK frequency: 26 to 56MHz
Built-in PLL and clock recovery

The LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller.
It is fully compliant with the JEDEC standard. Optimized for low-power and high-speed applications, it ensures robust timing and a small silicon area.
The PHY IP contains specialized functions to guarantee high-performance I/Os, critical timing, low power and jitter with programmable fine-grain control for any SDRAM interface.

The PCIe-NVMe SSD controller platform is compliant with NVM Express 1.2 specification and targets for both enterprise and client SSD markets.
It features YEESTOR's NVMe controller core and LDPC error correction core to enable low-power and cost-effective SSD controllers that support 1x/1y/1z MLC/TLC and 3D NAND.

The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips.
It is designed with scalability in mind and provides standard AXI interface for the ease of integration in SoC design.
The NFC has many configurable features to support the requirements for different NAND Flash applications.

The NVMe controller core (Meissa) is compliant with NVM Express 1.4 specification (NVMe 2.0 Mandatory) and targeted for both enterprise and client SSD markets.
It is a highly hardware automated design that requires minimum SW/FW involvement from the CPU.
It supports out of order IO read data transfer and can boost the IOPS performance and minimize the latency of SSD controllers.

The ApSRAM controller is a flexible, low-power, and low-latency solution designed for SRAM replacement in high-performance systems.
Scalable from 64Mb to 1Gb, its multi-bank architecture enhances timing throughput, making it ideal for wearables, IoT devices, displays, automotive systems, industrial automation, and consumer electronics.
Optimized for AI/ML, edge computing, and high-performance embedded systems, it supports seamless integration through its configurable AXI interface and adaptability across FPGA, Gate array, and Standard cell technologies.

Compliant to JEDEC DDR5 SDRAM Specification, Data Buffer & RCD Specification.
Supports connection to any DDR5 Memory Controller IP communicating with a JEDEC compliant DDR5 Memory Model.
Supports configurable SDRAM addressing of different sizes (x4, x8 and x16).
Available in all memory sizes up to 64 Gb.
Supports for all speed-grades/speed-bins.

The DDR5 RDIMM Verification IP provides an effective & efficient way to verify the components interfacing with DDR5 RDIMM interface of an ASIC/FPGA or SoC.
The DDR5 RDIMM VIP is fully compliant with Standard DDR5 specification from JEDEC.
This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

The HBM4 Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASIC/FPGA or SoC.
The HBM4 VIP is fully compliant with Standard HBM Version JESD270-4 specifications from JEDEC.
This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

The LPDDR6 Verification IP provides an effective & efficient way to verify the LPDDR6 components of an IP or SoC.
The VIP is lightweight, featuring easy-to-use plug-and-play components, so there is no impact on the design cycle time.