IP Catalog > Memory Controller/PHY IP

Memory Controller/PHY IP

Memory Interface IP cores support a wide range of memory types and standards, including DDR IP (Double Data Rate), GDDR IP (Graphics Double Data Rate), HBM IP (High Bandwidth Memory), and LPDDR IP (Low Power DDR), ensuring optimal performance in applications such as gaming, data centers, and mobile devices. NVM Express IP offers high-speed, low-latency storage interface for solid-state drives, while ONFI IP supports NAND flash memory communication. Additionally, SAS IP (Serial Attached SCSI) and SATA IP (Serial ATA) enable reliable, high-performance storage solutions, and SD/eMMC IP cores facilitate efficient data transfer for embedded systems.

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Search (1,337)
Compare 1,337 Memory Controller/PHY IP from 78 vendors (1 - 10)
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
    • Supports Both NV-DDR3 and NV-LPDDR4 with 4-tap DFEs
    • Support Decision Feedback Equalization (DFE): For extra high loading, DFE can reduce errors and improve data integrity
    • Compliant with JEDEC 6.0 (TBD) and JESD 230G specifications
    • Supports real-time PVT data-eye monitoring
    Block Diagram -- 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
  • HBM3 Controller
    • The HermesCORE High-Bandwidth Memory Generation 3 (HBM3) controller is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high memory bandwidth, lower latency, and more density.
    • The controller can be delivered as part of a complete HBM3 memory subsystem with an integrated HBM3 PHY.
    Block Diagram -- HBM3 Controller
  • HBM3 PHY
    • Offers superior power efficiency and supports up to 4 active operating states and dynamic voltage scaling. With a fully optimized hard macro design on advanced process technology,
    • Delivers highly reliable industry-leading performance.
    • Implements an optimized micro bump array and is delivered as hard macro GOS ready for integration into 2.5D system applications.
    Block Diagram -- HBM3 PHY
  • UHS-II PHY Core IP
    • The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
    • It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
    • To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
    Block Diagram -- UHS-II PHY Core IP
  • UFS 4.0 Host
    •  UFS 4.0 (JESD220F.pdf)
    •  UFS HCI 4.0 (JESD223E.pdf)
    •  MIPI UniPro version 2.0(mipi_UniPro_specification_v2-0.pdf)
    •  MIPI M-PHY version 5.0(mipi_M-PHY_specification_v5-0.pdf)
    Block Diagram -- UFS 4.0 Host
  • UFS 3.1 host
    • The Universal Flash Storage 3.1 (UFS 3.1) is a simple but high-performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.
    Block Diagram -- UFS 3.1 host
  • UFS 3.0 Host
    • UFS 3.0 Host and Device configurations available
    • Complete UFS 3.0 hardware implementation
    • Interop-proven UniPro 1.8 link layer
    • MIPI M-PHY 4.0 Interface
    Block Diagram -- UFS 3.0 Host
  • UFS 2.1 Stack & Driver
    • Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6
    • Portability in choice of OS, processors and hardware
    • Easy-to-use interface for applications
    • Fully documented generic device operation API
    Block Diagram -- UFS 2.1 Stack & Driver
  • UFS 2.1 Host Controller IP
    • JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
    • Supports high performance M-PHY v3.0 type-1
    • 2 lanes @ 5.9 Gbps per lane
    • UniPro v1.6 link layer
    • Definable write-protect group size
    Block Diagram -- UFS 2.1 Host Controller IP
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