IP Catalog > Memory Controller/PHY IP

Memory Controller/PHY IP

Memory Interface IP cores support a wide range of memory types and standards, including DDR IP (Double Data Rate), GDDR IP (Graphics Double Data Rate), HBM IP (High Bandwidth Memory), and LPDDR IP (Low Power DDR), ensuring optimal performance in applications such as gaming, data centers, and mobile devices. NVM Express IP offers high-speed, low-latency storage interface for solid-state drives, while ONFI IP supports NAND flash memory communication. Additionally, SAS IP (Serial Attached SCSI) and SATA IP (Serial ATA) enable reliable, high-performance storage solutions, and SD/eMMC IP cores facilitate efficient data transfer for embedded systems.

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Search (1,341)
Compare 1,341 Memory Controller/PHY IP from 78 vendors (1 - 10)
  • Verification IP for UFS
    • Avery UFS/Unipro VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates: constrained random SCSI and Unipro traffic generation, robust packet and physical layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging, and performance analysis metrics.
    Block Diagram -- Verification IP for UFS
  • Verification IP for HBM
    • HBM VIP is a comprehensive memory VIP solution portfolio for high bandwidth memory (HBM), targeting a new standard in memory performance, density, power consumption, and cost.
    • HBM VIP is intended for SoC and memory control ler designers who employ external HBM modules and PHY developers to ensure both comprehensive verification and protocol and timing compliance.
    Block Diagram -- Verification IP for HBM
  • Verification IP for NVMe
    • Accelerated confidence in simulation-based verification of RTL designs with NVMe interfaces over PCIe or Fabric links
    Block Diagram -- Verification IP for NVMe
  • ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
    • Support ONFi 4.0 IO Electrical Specification
    • Support Legacy up to 50MHz
    • Support NV-DDR2 with operating frequency up to 533Mbps
    • Support NV-DDR3 with operating frequency up to 800Mbps
    Block Diagram -- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
    • Supports Both NV-DDR3 and NV-LPDDR4 with 4-tap DFEs
    • Support Decision Feedback Equalization (DFE): For extra high loading, DFE can reduce errors and improve data integrity
    • Compliant with JEDEC 6.0 (TBD) and JESD 230G specifications
    • Supports real-time PVT data-eye monitoring
    Block Diagram -- 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
  • HBM3 Controller
    • The HermesCORE High-Bandwidth Memory Generation 3 (HBM3) controller is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high memory bandwidth, lower latency, and more density.
    • The controller can be delivered as part of a complete HBM3 memory subsystem with an integrated HBM3 PHY.
    Block Diagram -- HBM3 Controller
  • HBM3 PHY
    • Offers superior power efficiency and supports up to 4 active operating states and dynamic voltage scaling. With a fully optimized hard macro design on advanced process technology,
    • Delivers highly reliable industry-leading performance.
    • Implements an optimized micro bump array and is delivered as hard macro GOS ready for integration into 2.5D system applications.
    Block Diagram -- HBM3 PHY
  • UHS-II PHY Core IP
    • The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
    • It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
    • To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
    Block Diagram -- UHS-II PHY Core IP
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