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Compare 2,942 Clocking IP from 75 vendors (1 - 10)
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
    • Rail-to-Rail IQ ADC Input Capability
    • 65dB IQ ADC SNR
    • Programmable Full-Scale IQ DAC Output Current
    • 65dB IQ DAC SNR
    Block Diagram -- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
  • 40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
    • TSMC 40nm CMOS
    • 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
    • Scalable Power Consumption
    Block Diagram -- 40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
  • 40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
    • 2.0GHz-to-4.7GHz PLL Output Coverage
    • Scalable Power Consumption
    Block Diagram -- 40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
  • 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
    • 16MHz-to-2GHz PLL Output Coverage
    • Scalable Power Consumption
    • Three independent programmable PLL outputs
    • Internal Calibration Engine and Convergence Algorithm
    Block Diagram -- 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • 4-Phase LC PLL on INTEL 16
    • High performance design for meeting low jitter requirements including Ref Clock applications
    • Implemented with Analog Bits’ proprietary LC architecture
    • Low power consumption
    • Integrated power supply regulation for low deterministic jitter
    Block Diagram -- 4-Phase LC PLL on INTEL 16
  • 18-40MHz Crystal Oscillator on INTEL-16
    • Crystal Oscillator pad macro that supports many industry standard crystals in the 18-40MHz range (e.g. 19.2, 24MHz, 25MHz, 38.4MHz)
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on INTEL-16
  • All Digital Phase Locked Loop
    • The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
    • Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
    Block Diagram -- All Digital Phase Locked Loop
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