Clocking IP

OSC-XT-32k-T12FFC.01_TSMC_12_FFC+ is an ultra-low power crystal-based oscillator in TSMC 12FFC+ for accurate 32 kHz clock generation in the SoC Always-On domain (eg. implementation of RTC features).
An embedded auxiliary loop controls the voltage amplitude at the crystal terminals for maximizing the power efficiency for multiple crystals.

OSC-RC-32k-LD-A01-T22ULL.01_TSMC_22_ULL is a 32 kHz RC oscillator in TSMC 22ULL specifically designed for the implemenation of accurate time-based features in always-on domains.
With an overall precision better than 500 ppm on its full voltage and temperature operating ranges, Dolphin's IP meets the sleep clock accuracy requirements of the BLE standard, removing the need for an external crystal.

OSC-RC-32k-A01-D18-T22ULL.03_TSMC_22_uLL1.8 is a 32 kHz RC oscillator in TSMC 22ULL with 1.8 V I/O MOSFET devices based on a low-power architecture for the implementation of always-on domains.
The IP informs the host when the frequency has reached a stable frequency value after leaving shutdown or standby mode.

The ODT-CRX-2P5G-16FFCT is a high-speed clock receiver circuit capable of operating up to 2.5 GHz with low output jitter.
The CRX uses a high-speed signal path that can provide low jitter for input ranges of up to 2.5 GHz input. It also features small area and low power consumption. It includes the decoupling capacitors and ESD protection diodes on the CLKIN pins.

Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.

180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
It consists of the following main sub-blocks: reference oscillator; main PLL loop: Fractional-N PLL and VCO blocks; secondary digital PLL loop: synchronization subsystem; dividers block: clock generation/delivery subsystem; voltage stabilizers.
High frequency synthesis is needed for both phase noise performance and ultra-fine frequency tuning step.

$Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer$

The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
High energy efficiency: Only 5 μW are consumed during operation
A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz