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Compare 2,956 Clocking IP from 75 vendors (1 - 10)
  • 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
    • 180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
    • It consists of the following main sub-blocks: reference oscillator; main PLL loop: Fractional-N PLL and VCO blocks; secondary digital PLL loop: synchronization subsystem; dividers block: clock generation/delivery subsystem; voltage stabilizers.
    • High frequency synthesis is needed for both phase noise performance and ultra-fine frequency tuning step.
    Block Diagram -- 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
  • 10MHz to 50MHz fractional-N PLL synthesizer
    • UMC 22nm ULP technology
    • 1.8V IO power supply
    • Double 0.8/1.0V Core power supply
    • Embedded low noise bias
    Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer
  • ULP Clock Generator - GLOBALFOUNDRIES 22FDX
    • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
    • High energy efficiency: Only 5 μW are consumed during operation
    • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
    Block Diagram -- ULP Clock Generator - GLOBALFOUNDRIES 22FDX
  • ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
    • Clock generation based on a Digitally Controlled Oscillator (DCO)
    • 800 MHz < = DCO frequency < = 2400 MHz
    • Programmable clock frequency dividers for ADPLL loop and clock outputs
    • lock-in < 25 us
    Block Diagram -- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
  • ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
    • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
    • High energy efficiency: Only 5 μW are consumed during operation
    • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
    Block Diagram -- ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
  • X-band (7.9 − 9.8GHz) High Performance Frac-N PLL
    • The NEXUS9X is a CMOS high performance PhaseLocked Loop (PLL) with integrated voltage controlled oscillator (VCO) and loop filter, designed to provide high flexibility in its use in order to adapt to a variety of applications.
    • It covers typically the frequency range [7.9 − 9.8]GHz over variations in process, voltage and temperature (PVT), which can be scaled up/- down by using frequency multipliers/dividers, depending on the application.
    Block Diagram -- X-band (7.9 − 9.8GHz) High Performance Frac-N PLL
  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
  • All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (sub 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 7mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (< 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 10mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
  • All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
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