Clocking IP

Compare 2,909 Clocking IP from 78 vendors (1 - 10)

PLL
- The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
- It can generate a stable high-speed clock from an ultra-wide input clock
- With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
Master/Slave DLL
- The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing
- This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint
- The DLL PHY is designed to generate precise phase-shifted clocks (e.g
- 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission
Low Power 300-600 MHz programmable PLL
- The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply
- This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz
- The VCO outputs are coming into 8 cascaded phases
- The PLL needs a sourcing current of 2 uA in order to operate
MEMS-based Clock Generator with On-chip Temperature Compensation
- The MVCLK02 is a high-precision and programmable clock generator circuit, with a wide output frequency range.
- The chip contains a versatile MEMS oscillator circuit that is designed to ensure high performance for a wide range of MEMS resonators and with different parameters.
General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Output frequency range: 500MHz – 2GHz
- Loop bandwidth 60kHz – 180MHz
- 8 or 4 phase output clocks
- Output clock duty cycle 50 +5%
- Typically locks within 150 reference clock cycles
- Simple power-up sequence
- Lock indicator signal
Clock Attack Monitor
- The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of critical circuits.
- agileCAM can detect attacks based on changes in clock frequency, clock hold and clock glitch errors.
- Additionally, it provides a relative frequency measurement of the monitored clock with programmable alarm thresholds.
32KHz Low Power Oscillator
- 850nW typical power @32KHz.
- Available frequencies 10KHz – 100KHz.
- No external components.
- 60ppm/°C temperature sensitivity.
- 0.3%/100mV vdd sensitivity.
- Base cell area 0.005mm².
Integrated Oscillator - TSMC 180n
- The OT3912t is an integrated oscillator for TSMC 180n processes.
- No external components are required. After a simple trim process a frequency stability of better than 1% is achieved over voltage and temperature ranges.
Low Power PLL for TSMC 40nm ULP
- Wide range M, P, and N integer dividers.
- 40MHz – 600MHz output frequency range.
- Input frequency range 1.4MHz – 32MHz.
- 18pS RMS cycle to cycle jitter.
- Lock-detect function.
- Optional bypass function.
General Purpose PLL for TSMC 152nm
- Wide range M integer divider. (See ot3122 for M, N, and P dividers)
- 40MHz – 800MHz output frequency range.
- Comparable frequency range 8MHz – 32MHz.
- Optional prescaler.
- 19pS RMS cycle to cycle jitter at 800MHz.
- Lock-detect function.
- Bypass function.
- 20µS well defined fast startup behavior.