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Clocking IP

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Compare 2,872 Clocking IP from 74 vendors (1 - 10)
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • 4-Phase LC PLL on INTEL 16
    • High performance design for meeting low jitter requirements including Ref Clock applications
    • Implemented with Analog Bits’ proprietary LC architecture
    • Low power consumption
    • Integrated power supply regulation for low deterministic jitter
    Block Diagram -- 4-Phase LC PLL on INTEL 16
  • 18-40MHz Crystal Oscillator on INTEL-16
    • Crystal Oscillator pad macro that supports many industry standard crystals in the 18-40MHz range (e.g. 19.2, 24MHz, 25MHz, 38.4MHz)
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on INTEL-16
  • All Digital Phase Locked Loop
    • The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
    • Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
    Block Diagram -- All Digital Phase Locked Loop
  • Multi-rate Audio DAC/PLL Core
    • Operates from single 27/54MHz clock.
    • Ideal for MPEG, AC-3, DVD systems
    • Internally generates audio sample clocks
    • Multi-sample rates: 32, 44.1, 48 KHz
    Block Diagram -- Multi-rate Audio DAC/PLL Core
  • ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
    • ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip
    • The Ultra-Low Voltage Clock Generator is targeted at Systems on Chip (SoCs) employing advanced power management techniques.
    • The robust, fully digital architecture allows operation in a wide voltage and frequency range. Unique fast lock and instant frequency change features maximize the energy efficiency of the targeted systems.
    Block Diagram -- ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
  • ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
    • The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
    • High energy efficiency: Only 5 μW are consumed during operation
    • A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
    Block Diagram -- ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Entirely core voltage powered, needs no analog supply voltage
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
  • 18-40MHz Crystal Oscillator on TSMC CLN2P
    • Crystal Oscillator pad macro that supports industry standard crystals
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on TSMC CLN2P
  • PLL
    • The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
    • It can generate a stable high-speed clock from an ultra-wide input clock
    • With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
    Block Diagram -- PLL
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