LCD Controller IP
Welcome to the ultimate LCD Controller IP hub! Explore our vast directory of LCD Controller IP
All offers in
LCD Controller IP
Filter
Compare
26
LCD Controller IP
from 10 vendors
(1
-
10)
-
TFT/LCD/MIPI Display Controller and Composition Engine
- Programmable display resolutions up to 32Kx32K
- Compressed framebuffer support
- Variable Frame-Rate support
-
Display Controller - LCD / OLED Panels (AHB-Lite Bus)
- Wide range of programmable LCD Panel resolutions:
- Support for 1 Port TFT LCD Panel interfaces:
- Programmable frame buffer bits-per-pixel (bpp) color depths:
- Programmable Output format support:
-
Display Controller - LCD 4K Digital Cinema (DCI)
- Support for following LCD Panel resolutions:
- 3840 x 2160 Quad / Ultra Full High Definition (QFHD)
- 4096 x 2160 Digital Cinema Systems (DCI)
- 2048 x 1080 Digital Cinema Systems (DCI)
-
BitBLT Graphics Hardware Accelerator (AHB Bus)
- Bit Block Transfer – 3 Independent Memory Sources of data:
- 2D Raster Operations (ROP) performed on Block Transfers:
- BitBLT Draw Features:
- 2D Graphics Rendering Engine (Option):
-
BitBLT Graphics Hardware Accelerator (AXI Bus)
- Bit Block Transfer – 3 Independent Memory Sources of data:
- 2D Raster Operations (ROP) performed on Block Transfers:
- BitBLT Draw Features:
- 2D Graphics Rendering Engine (Option):
-
AXI Bus Display Controller
- Wide range of programmable Display Panel resolutions:
- Releases supporting baseline display requirements and releases with following
- optional display processing features:
- Color Palette RAM per layer or single Palette for integrated display image
-
Multilayer Configurable Display Controller
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096x4096
- Completely variable timing parameters, for standard or specific display resolutions
- Support for 8,16, 18 or 24 bit RGB output color depth
-
FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
- 1 & 2 Port LVDS Panels
- Supports 3 and 4 data and 1 clock LVDS differential pairs
- 18 / 24 bits-per-pixel (typically RGB or YCbCr)
-
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
- Bit Block Transfer – 3 Independent Memory Sources of data:
- 2D Raster Operations (ROP) performed on Block Transfers:
- BitBLT Draw Features:
- 2D Graphics Rendering Engine (Option):
-
Lightweight Configurable Display Controller
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096×4096
- Completely variable timing parametersfor standard or specific display resolutions
- Support for 8,1618 or 24 bit RGB output color depth
