LCD Controller IP

The AHB TFT LCD Controller is a configurable core that interfaces to an AHB microprocessor bus and provides all the timing control and pixel serialization for controlling various TFT LCD Display Panels.
The core can also be used with various RAMDACs to interface to VGA Monitors or VGA style LCD Panels.
The AHB TFT LCD Controller supports 24-bit true color and 16-bit color, as well as an 8-bit color display mode via the 256 Pixel Palette Ram.

The DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus within Altera Qsys Integration (generating the System Interconnect Fabric) to a TFT LCD panel.
In an Altera FPGA, typically, the microprocessor is a NIOS II or ARM processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.

The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to an 4K/8K TFT LCD / OLED display panel.
The video image in frame buffer memory can be 8/10/12-bit 4:2:0 or 4:2:2 or 4:4:4 sampled YCrCb video or 4:4:4 RGB. For 4:2:0 and 4:2:2 YCrCb, the chroma components are re-sampled to 4:4:4 and color converted to RGB.

The DB6845 CRT Controller core is a full function equivalent to the Motorola MC6845 device.
The DB6845 interfaces a microprocessor to a raster-scan CRT display. The microprocessor access 19 registers (1 Address and 18 Data Registers) within the DB6845 in order to provide video timing, refresh memory addresses, cursor, and light pen strobe signals.
CRT video timing signals include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.

The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).

The DB-FPD-LVDS-TX LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 or 5 LVDS Differential Data Pairs and 1 LVDS Differential Clock Pair.

The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.

The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
The DB9100AXI also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.

The DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
The DB9100AHB also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps.
A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.