DisplayPort IP

The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures.
With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification.
This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.

VESA DisplayPort 1.4 compliant
Reed-Solomon RS (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
DisplayPort main 8b/10b encoder included (Tx only)
Status and control can be done with signals or optionally via an integrated APB register module (Rx)

Compliant to Display Port 2.0/eDP1.5.
Dynamic support for RGB / YCbCr444 / YCbCr422 / RAW and Y only formats.
Supports multi-stream transport (MST) upto 4 streams and single stream transport (SST).
Dynamic lane support (1, 2, or 4 lanes).

Supported link rates of 1.62, 2.7 and 5.4 Gbps.
Hardware proven.
Simulation testbench.
Example project, including firmware which performs link initialization with the PHY

Fully compliant with VESA Embedded DisplayPort (eDP) Standard 1.5 Specification
Supports power saving feature:- Panel Self Refresh features PSR/PSR2, PR, Adaptive sync, and backlight control.
Supports HDCP version 1.4, 2.2 and 2.3
Supports Alternative Scrambler Seed Reset (ASSR)
- TPS4 with ASSR is supported

Supports Isochronous transport services over the Main-Link.
Capable Link and device management services over the AUX_CH.
Can handle AUX transaction to access the DisplayPort Configuration Data (DPCD) address.
Capable of handling multi stream packet and single stream packet data transmission.

Silicon proven on multiple ASIC and FPGA processes
Capable of operating without a host CPU in low complexity applications
Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes

Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort 1.5.
Features include link rates up to 20Gbps for DisplayPort 2.0, 8.1Gbps for DisplayPort 1.4a. Display Steam Compression (DSC), multi-stream transport (MST) and more. The base core includes all required link functionality— Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 2.3 standards for data encryption.