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Serdes IP

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Search (151)
Compare 151 Serdes IP from 30 vendors (1 - 10)
  • High-Speed LVDS (SERDES) Transceiver
    • The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
    • The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.
    Block Diagram -- High-Speed LVDS (SERDES) Transceiver
  • Combo SerDes
    • 4 Channels per Quad
    • Data rate up to 25/28/32Gbps
    • Shared Quad LC-PLL for high performance
    • Independent Ring-PLL of each channel for clock flexibility
    Block Diagram -- Combo SerDes
  • Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
  • 64G SerDes
    • 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
    • Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
    • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
    • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
    Block Diagram -- 64G SerDes
  • 112G SerDes USR & XSR
    • 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
    • Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
    • Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
    • Digitally-control-impedance termination resistors
    Block Diagram -- 112G SerDes USR & XSR
  • Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
    • The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.
    Block Diagram -- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
  • Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) IP
    • Most Likely Sequence Detector(MLSD)
    • High speed A/D
    • Sub-sampling clock multiplier
    • Master Controller
    Block Diagram -- Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) IP
  • Long-Reach (LR) Multi-Standard-Serdes (MSS) IP
    • High speed A/D
    • Sub-sampling clock multiplier
    • Master controller
    Block Diagram -- Long-Reach (LR) Multi-Standard-Serdes (MSS) IP
  • 4.25 Gbps Multi-Standard SerDes
    • The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
    Block Diagram -- 4.25 Gbps Multi-Standard SerDes
  • Ultra-short reach SerDes with 500 Gbit/s throughput
    • 2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
    • High pin-efficiency and low power
    • 208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)
    Block Diagram -- Ultra-short reach SerDes with 500 Gbit/s throughput
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