Coprocessor IP
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BitBLT Graphics Hardware Accelerator (AXI Bus)
- The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
- A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
- The DB9100AXI also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.
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Scalable and Programmable Co-processor
- Hardware scalability to offer the best cost-performance trade-off
- Programmable Software-defined solution for flexible DSP components
- Enables complex DSP and high data-rate communication system design
- Can be optimized for FPGA and ASIC targets
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Constant False Alarm Rate Processor (CFAR)
- Removes a compute intensive task away from the microprocessor to a predictable, low-latency offload engine
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ADPCM G.726 Codec
- Compliant with ITU G.721, G.723, G.726 and G.726-Annex recommendations.
- On-the-fly configuration for variable compression rate, PCM law.
- Process capability of up to 64 full duplex or up to 128 half duplex voice channels.
- Burst and continuous mode support.
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ITU-T G729A Voice Codec Hardware Accelerator
- Voice codec capable of multi-channel 8kbps voice compression based on ITU-T G729A standard.
- Selective Channel initialization.
- AMBA bus support for easy SoC integration.
- Best performance/silicon area ratio available in the industry.