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Error Correction/Detection IP

Error Correction/Detection IP cores are specialized hardware modules designed to enhance the reliability and integrity of data transmission and storage in embedded systems. These cores implement advanced error detection and correction algorithms, such as Hamming codes, Reed-Solomon, and BCH, to identify and correct errors in data, ensuring accurate and secure communication. Ideal for applications in memory systems, communication networks, and high-performance computing, Error Correction/Detection IP cores help prevent data corruption, reduce system downtime, and improve overall system performance.

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Search (249)
Compare 249 Error Correction/Detection IP from 40 vendors (1 - 10)
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
  • LDPC Encoder/Decoder (LDPC)
    • Supporting a wide range of data-rates
    • 50MB/s to 4.0GB/s for a single LDPC instance
    • Scalable platform provides the basis for customer specific custom-LDPC cores
    Block Diagram -- LDPC Encoder/Decoder (LDPC)
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
  • Reed Solomon FEC
    • Designed to support any Reed Solomon code.
    • Custom tailored to support specific codes see standard table below
    • Low Latency
    • FEC Processing cycles optimized for reduced buffering
    Block Diagram -- Reed Solomon FEC
  • LDPC Encoder/Decoder IP Core
    • IPM-LDPC for NandFlash Storage: Adaptable BER, Up to 6 checks per bit, customizable data path
    • IPM-LDPC for short code: option to be full asynchronous, option to be in 3 clock cycles
    • fully configurable: matrix generator, data path, number of iteration checks, packet size
    Block Diagram -- LDPC Encoder/Decoder IP Core
  • LDPC (1723,2048) IIP
    • Compliant with IEEE Standard 802.3.2018 Ethernet specification.
    • Supports full LDPC functionality.
    • Supports the Lower density parity check (1723,2048).
    • Supports the parity generation of 325 bits.
    Block Diagram -- LDPC (1723,2048) IIP
  • FEC RS (544,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (544,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (544,514) IIP
  • FEC RS (528,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (528,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (528,514) IIP
  • FEC RS (255,251) IIP
    • HDMI specification 2.1/2.1a and Scalabale Low Voltage Signaling with Embedded Clock (SLVS_EC) compliant.
    • Supports full FEC functionality.
    • Supports Reed Solomon (255,251) FEC, 8-bit symbols.
    • Supports the input and output data widths of multiples of 8-bit.
    Block Diagram -- FEC RS (255,251) IIP
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