IP Catalog > DSP & Math IP > Error Correction/Detection IP

Error Correction/Detection IP

Error Correction/Detection IP cores are specialized hardware modules designed to enhance the reliability and integrity of data transmission and storage in embedded systems. These cores implement advanced error detection and correction algorithms, such as Hamming codes, Reed-Solomon, and BCH, to identify and correct errors in data, ensuring accurate and secure communication. Ideal for applications in memory systems, communication networks, and high-performance computing, Error Correction/Detection IP cores help prevent data corruption, reduce system downtime, and improve overall system performance.

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Search (236)
Compare 236 Error Correction/Detection IP from 38 vendors (1 - 10)
  • 66/2112 Codec for Cyclic Code (2112,2080)
    • Small Size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    Block Diagram -- 66/2112 Codec for Cyclic Code (2112,2080)
  • 2.5 Gbps GPON FEC Codec
    • This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications.
    • It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation.
    • The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module.
    Block Diagram -- 2.5 Gbps GPON FEC Codec
  • WCDMA Release 9 compliant Viterbi Decoder
    • 3GPP TS 25.212 V 9.5.0 Release 9
    • Supports all block sizes i.e., K=40 - 504.
    • Constraint length of 9
    Block Diagram -- WCDMA Release 9 compliant Viterbi Decoder
  • Block Diagram -- Error Correction IP
  • DVB-Satellite FEC Decoder
    • The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
    • The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.
    Block Diagram -- DVB-Satellite FEC Decoder
  • oFEC Encoder and Decoder
    • OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
    • The oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach.
    Block Diagram -- oFEC Encoder and Decoder
  • SDA OCT Encoder and Decoder
    • ​Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-001-05, August 2021"
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.1.0, Document ID: SDA-9100-001-08, March 2024"
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 4.0.0, Document ID: SDA-9100-001-09, August 2024"
    Block Diagram -- SDA OCT Encoder and Decoder
  • DVB-S2-LDPC-BCH IP
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
    Block Diagram -- DVB-S2-LDPC-BCH IP
  • Block Diagram -- BCH Encoder and Decoder IP Core
  • FEC RS (528,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (528,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (528,514) IIP
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