Telco/OTN IP

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Compare 61 Telco/OTN IP from 10 vendors (1 - 10)
  • Universal G704-E1 Framer / Deframer Core
    • The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
    • Transmit and receive part are designed as individual blocks, both independently handle basic and multi frames.
    Block Diagram -- Universal G704-E1 Framer / Deframer Core
  • SONET/SDH OC-3 Transceiver/CDR
    • The SMS2011 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration on a single IC in a typical System-On-Chip (SOC) application.
    • SMS2011 interfacing to the rest of building blocks on chip is fully customizable. For example, an optional mux demux module can be interconnected to the SMS2011 core making it capable of performing all the necessary serial-to-parallel and parallel to-serial functions in compliance with SONET/SDH transmission standards.
    Block Diagram -- SONET/SDH OC-3 Transceiver/CDR
  • SONET/SDH OC-12 Transceiver/CDR
    • The SMS2012 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration on a single IC in a typical System-On-Chip (SOC) application.
    • SMS2012 interfacing to the rest of building blocks on chip is fully customizable. For example, an optional mux demux module can be interconnected to the SMS2012 core making it capable of performing all the necessary serial-to-parallel and parallel to-serial functions in compliance with SONET/SDH transmission standards.
    Block Diagram -- SONET/SDH OC-12 Transceiver/CDR
  • TCP/TCPSW Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides TCP as per RFC-9293 specification
      • Supports TCP connection establishment and closing connection
      • Supports TCP Flow Control
      • Supports Checksum Calculation and checksum error detection
      • Supports TCP Header creation and parsing
      • Supports Separation of TCP/nonTCP packets Encodes and decodes TCP headers
      • Supports unicast delivery of data
      • Bidirectional/unidirectional dataflow is supported over TCP connections
    • Supports TCP connection establishment and closing connection
    • Supports TCP Flow Control
    Block Diagram -- TCP/TCPSW Verification IP
  • OSU processor, optimized for E1/FE/GE services with Ethernet over SDH over OTU0/OTU1 lines
    • Line Signals: 2x OTU0/1
    • Protection: 1+1 at the OTU/ODU/OSU/VC levels
    • Integrated HDLC controllers for GCC channels
    Block Diagram -- OSU processor, optimized for E1/FE/GE services with Ethernet over SDH over OTU0/OTU1 lines
  • OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines
    • Supports NG-OTN
    • 2x OTU0/OTU1 Line-Side OTN
    • 4x FE/GE/STM1/STM4 and 4x E1 client-services
    • Alarms Monitoring and Performance Counters on lines and client-services
    Block Diagram -- OSU/OTN processor, optimized for E1/STM1/OC3/STM4/OC12/FE/GE services over OTU0/OTU1 lines
  • 100G OTN Transponder with AES
    • Line Interface
    • Client Interface
    • PMA/PCS
    • Ethernet Media Access Control (MAC) + RS Link ( Optional )
    Block Diagram -- 100G OTN Transponder with AES
  • 400G OTN Transponder with AES
    • Line Interface
    • Client Interface
    • OTN Mapper +GFEC
    • OTN De-mapper +GFEC
    Block Diagram -- 400G OTN Transponder with AES
  • 40G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 40G OTN Digital Wrapper
  • 100G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 100G OTN Digital Wrapper
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