DMA Controller IP
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The Direct Memory Access (DMA) controllers enable the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.
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DMA Controller IP
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DMA Controller IP
from 14 vendors
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AMBA AHB Direct Memory Acess (DMA) Controller
- Multiple independent DMA channels with direct AHB bus interface.
- DMA transfers between AHB memory devices and I/O ports.
- Scatter-gather allows DMA to merge multiple data source to contiguous space.
- Supports both hardware initiated transfer and software initiated transfer.
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DMA Controller
- Multiple independent DMA channels
- Designed with synthesizable HDL for ASIC and PLD implementations in variou system environments
- Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
- Supports both hardware initiated transfer and software initiated transfers.
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AMBA AHB 4 Channel DMA Controller
- The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
- The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
- The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
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AHB Single Channel DMA Controller
- The AHB Single Channel DMA Controller core is a configurable single channel direct memory access controller.
- The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
- The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.
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AXI4-Stream to/from AXI Memory Map - AXI Memory Map Conversion to AXI4-Stream, 16 Channels
- The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to an AXI4-Stream TID, and sends the data with TID out on the AXI4-Stream Interface.
- The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE IP Core works with Digital Blocks DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from either memory or a peripheral to an AXI4-Stream peripheral or AXI4 Stream Network Interface.
- The companion IP, the DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE, works with Digital Blocks DMA Controller to transfers data from an AXI4-Stream peripheral or AXI4-Stream Network Interface to memory or another peripheral.
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AXI4-Stream to/from AXI Memory Map - AXI4-Stream Conversion to AXI Memory Map, 16 Channels
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The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE IP Core works with the DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from an AXI4-Stream peripheral or AXI4-Stream Network Interface to either memory or another peripheral.
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SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
- The DB-DMAC-MC-AHB5 & DB-DMAC-MC-AHB-Lite Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
- The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB Master Read/Write interconnects.
- The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16.
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SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
- The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
- The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with user selectable AMBA AXI4 / AXI3 Master Read/Write interconnects.
- The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, 16.
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AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
- The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
- Descriptor Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interface, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
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AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
- The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
- Control is managed by Descriptors initialized by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.