DMA Controller IP

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The Direct Memory Access (DMA) controllers enable the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.

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Compare 31 DMA Controller IP from 14 vendors (1 - 10)

General Purpose & Bridge DMA
- DMA-GP Core
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
- 2 Dedicated DMA Channels, 1 each for data transfers for the following:
- Command and Status via AXI4-Stream Interfaces - 1 set per MM2S & S2MM:
- MM2S & S2MM DMA Controllers:
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- 2 Dedicated DMA Channel
- Command and Status via Scatter Gather List (SGL)
- Arbiter – Round Robin
Peripheral Direct Memory Access Controller
- AMBA AXI4-Lite slave bus
- AMBA AXI4 master bus
- Configurable number of peripheral channels
- 8, 16, 32 bits data transfer modes
Peripheral Direct Memory Access Controller
- AMBA APB3 slave bus
- AMBA AHB-Lite master bus
- Configurable number of peripheral channels
- 8, 16, 32 bits data transfer modes
DMA Controller with TileLink IIP
- Supports 1-16 channel DMA Transmit and DMA Receive Engine
- Compliant with TileLink specification v1.7.1
- Supports access for Ring and Chained Descriptor Structures
- Configurable Transmit and Receive Engine based on Host Memory Data Width
DMA Controller with OCP IIP
- Supports 1-16 channel DMA Transmit and DMA Receive Engine
- Compliant with OCP 3.1 specification
- Supports access for Ring and Chained Descriptor Structures
- Configurable Transmit and Receive Engine based on Host Memory Data Width
DMA Controller with AXI IIP
- Supports 1-16 channel DMA Transmit and DMA Receive Engine
- Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
- Supports access for Ring and Chained Descriptor Structures
- Configurable Transmit and Receive Engine based on Host Memory Data Width
DMA Controller with AHB IIP
- Supports 1-16 channel DMA Transmit and DMA Receive Engine
- Compliant with ARM AMBA 2 AHB Specification
- Optional support for AMBA 3 AHB-Lite and AMBA 5 AHB Specification
- Supports access for Ring and Chained Descriptor Structures
AXI4 to/from Stream DMA
- Independent stream-to-memory, and memory-to-stream paths
- Up to 16 commands per direction with 32-bit or 64-bit address offset and 16-bit transfer length