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JESD204 IP

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Compare 39 JESD204 IP from 12 vendors (1 - 10)
  • JESD204B UVM VIP
    • The vendor provides configurable JESD204B TX/RX verification IP
    • JESD204B is a Serial Interface for Data Converters which are defined by JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
    • Our VIP covers Transport and Data link layer functionality of JESD204B
    • The VIP provides more flexible configuration to user to select their needs like lane,device configuration, data width
    Block Diagram -- JESD204B UVM VIP
  • JESD204 Verification IP
    • This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
    • The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product.
    Block Diagram -- JESD204 Verification IP
  • JESD204D Controller IP
    • Line rates up to 116 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    • HD-mode supported
    Block Diagram -- JESD204D Controller IP
  • JESD204C Controller IP
    • Designed to JEDEC JESD204C.1 specification
    • Line rates from 1 Gbps to 32.5 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204C Controller IP
  • JESD204B Controller IP
    • Designed to JEDEC JESD204B.01 specification
    • Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 16 Gbps)
    • Supports 1-24 lanes
    • Supports 1-96 converters
    Block Diagram -- JESD204B Controller IP
  • JESD204B/204C IP with PHY and MAC layer
    • X4/X8 Lane Mode, support up to 25Gbps (per lane)
    • Shared common PLL based architecture
    • Digitally-control-impedance termination resistors and On-chip resistance calibration
    • Configurable TX output differential voltage swing
    Block Diagram -- JESD204B/204C IP with PHY and MAC layer
  • Simulation VIP for JESD204
    • Topology
    • Transmitter or receiver configuration
    • Clock Frequency
    • Any frequency is supported, as the VIP works on the source clock
    Block Diagram -- Simulation VIP for JESD204
  • JESD403 VIP
    • Compliant with JESD403 version 1.0 specification.
    • Full JESD403 Host Controller and Device functionality.
    • Two wire serial interface up to 12.5 MHz.
    • Supports Dynamic Address Assignment including Static Addressing for legacy I2C Devices.
    Block Diagram -- JESD403 VIP
  • JESD207 Verification IP
    • Supports JESD207 specification.
    • Operates as BBIC (Baseband IC) and RFIC (Radio front end IC) monitor.
    • Supports half duplex data transfer.
    • Supports DDR source synchronous data transfer timing.
    Block Diagram -- JESD207 Verification IP
  • JESD204 Verification IP
    • Follows JESD204 specification JESD204A, JESD204B, JESD204C and JESD204D.
    • Supports Transmitter and Receiver Mode.
    • Supports data interfaces up to 116 Gbps with PAM4 and up to 58 Gbps with PAM2 in PHY layer.
    • Supports up to 32 lanes.
    Block Diagram -- JESD204 Verification IP
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