Interface Security IP
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Interface Security IP
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75
Interface Security IP
from 18 vendors
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10)
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Message filter
- Message filters are placed in the middle of a TCP / TLS session to scan application data, and discard unwanted messages and security-issue packets, reducing unnecessary traffic without increasing CPU load or latency.
- Unlike filters by IP address or port, which scan the data content and discard or pass through packets, DPI (Deep Packet Inspection) and other methods tend to cause CPU processing load and packet processing delays.
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SSL/TLS Offload Engine
- Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and authentication in SSL / TLS by combining our TCP offload and crypt engine.
- Since the record layer processing is completely hardware offloaded, the user application can overwhelmingly reduce the CPU load which only needs preparing the data to transfer securely.
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MacSec Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
- Provides MacSec as per IEEE standard 802.1AE-2018 specification
- Supports controlled and uncontrolled ports
- Encodes and decodes MacSeC PDUs
- Protects and validates macSec Pdus using AES-GCM-128 Cipher suites
- Cryptographic protection
- Modification and Addition of MSDU
- Uses configurable secure association key for encryption and authentication
- Supports Vlan and jumbo frames
- Supports Replay protection and ICV Works in tandem with gPTP (IEEE 802.1AS)/ PTP (IEEE 1588)
- Supports controlled and uncontrolled ports
- Encodes and decodes MacSeC PDUs
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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DDR Encrypter
- Protect the external memory
- On-the-fly encryption
- Optional authentication
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Memory & Bus Protection IP Core
- The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
- It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache. It is typically placed between the processor(s) and an external memory controller (DDRx).
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Crypto Coprocessor (Compact)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Crypto Coprocessor (Premium)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Crypto Coprocessor (Standard)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Inline Decrypter IP Core
- XIP (eXecution In Place) of encrypted code directly from Flash. (Optional xSPI controller)
- Decryption based on AES fully compliant with NIST FIPS 197
- AMBA Master/Slave interfaces
