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Cryptography IP

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Search (339)
Compare 339 Cryptography IP from 61 vendors (1 - 10)
  • PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
    • eSi-Crystals is a hardware core for accelerating the high-level operations specified in the NIST FIPS 202, FIPS 203 and FIPS 204 standards.
    • It supports the Cryptographic Suite for Algebraic Lattices (CRYSTALS), it is lattice-based digital signature algorithm designed to withstand attacks from quantum computers, placing it in the category of post-quantum cryptography (PQC). 
    Block Diagram -- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
  • ECC7 Elliptic Curve Processor for Prime NIST Curves
    • Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part of the “Suite B” of cryptographic algorithms approved by the NSA.
    • The design is fully synchronous, with the exception of the seed part, and available in both source and netlist form.
    • The core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
    Block Diagram -- ECC7 Elliptic Curve Processor for Prime NIST Curves
  • RSA2-AHB Accelerator Core with AHB Interface
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the AHB interface.
    Block Diagram -- RSA2-AHB Accelerator Core with AHB Interface
  • Scalable RSA and Elliptic Curve Accelerator
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the interface.
    Block Diagram -- Scalable RSA and Elliptic Curve Accelerator
  • SHA1, SHA2 Cryptographic Hash Cores
    • Completely self-contained; does not require external memory
    • SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2.
    • HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input.
    • Flow-through design; flexible data bus width
    Block Diagram -- SHA1, SHA2 Cryptographic Hash Cores
  • SNOW 3G Encryption Core
    • Keystream generation using the SNOW 3G Algorithm
    • High throughput: up to 7.5 Gbps in 65 nm process
    • Small size: from 7.5K ASIC gates
    • Satisfies ETSI SAGE SNOW 3G specification
    Block Diagram -- SNOW 3G Encryption Core
  • True Random and Pseudorandom Number Generator
    • Satisfies Federal Information Processing Standard (FIPS) Publication 140-2 Annex C (“approved” random number generator) from the US National Institute of Standards and Technology (NIST). Passes the requirements of the NIST SP 800-22.
    • High security (128 bit entropy; 256 version available)
    • Initial seed provided from internal entropy source
    • Automatic re-seeding
    Block Diagram -- True Random and Pseudorandom Number Generator
  • Cryptographically Secure Pseudo Random number Generator IP Core
    • Generates cryptographically secure pseudo-random numbers
    • Uses the CTR_DRBG algorithm per NIST publication SP800-90
    • Generates 128-bit data blocks with 8, 16, 32, 64 or 128-bit wide data interface
    • Provides security strength of 128,192 and 256 bits
    Block Diagram -- Cryptographically Secure Pseudo Random number Generator IP Core
  • NIST AES Key Wrap/Unwrap Core
    • Small size: AKW1 starts from less than 8,000 ASIC gates
    • Completely self-contained: does not require external memory
    • Supports both encryption (wrap) and decryption (unwrap). Encryption-only and decryption only versions available.
    • Includes AES key expansion
    Block Diagram -- NIST AES Key Wrap/Unwrap Core
  • Ultra-Compact Data Encryption Standard (DES/3DES) Core
    • Encrypts and decrypts using the DES / TDEA / Triple DES / 3DES Block Cipher Algorithm
    • High throughput: up to 3 Gbps at 750 MHz in 90 nm LV technology
    • Small size: from 3K ASIC gates for a triple DES core
    • Satisfies FIPS 46-3 from the US National Institute of Standards and Technology (NIST)
    Block Diagram -- Ultra-Compact Data Encryption Standard (DES/3DES) Core
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