IP Catalog > Security IP > Cryptography IP

Cryptography IP

Welcome to the ultimate Crypto Accelerator IP hub! Explore our vast directory of Crypto Accelerator IP
All offers in Cryptography IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (337)
Compare 337 Cryptography IP from 62 vendors (1 - 10)
  • 800G/400G/200G/100G AES Encryption Core
    • The 800G/400G/200G/100G AES Encryption Core is a high performance—yet low footprint—AES engine for 800/400/200/100 Gbps applications.
    Block Diagram -- 800G/400G/200G/100G AES Encryption Core
  • 100G AES Encryption Core
    • The 100G AES Encryption Core is a high performance—yet low footprint—AES engine for 100 Gbps applications.
    • Typical applications are providing bulk encryption for 100GE, LO ODUCn and OTU4.
    Block Diagram -- 100G AES Encryption Core
  • 50G/40G/25G/10G AES Encryption Core
    • The 10G/25G/40G/50G AES Encryption Core is a high performance—yet low footprint—AES engine for 10 Gbps to 50 Gbps applications.
    • Typical applications include providing bulk encryption for 25GE, 10GE, OTU3, OTU2 and OTU2e as well as legacy SONET/SDH OC192/STM-64 environments.
    Block Diagram -- 50G/40G/25G/10G AES Encryption Core
  • Sub-2.5G AES Encryption Core
    • The sub-2.5G AES Encryption Core is a special low footprint and low-power implementation of AES engine for application requiring less than 2.5G/s.
    • Because of its tiny footprint and low power, it works exceptionally well in system utilizing Gigabit Ethernet, fiber channel, custom linkage using RSlink/ethernet, GFP, dedicated VPN links, OTU1 and SONET/SDH OC48/12/3 and STM-16/4/1 environment.
    Block Diagram -- Sub-2.5G AES Encryption Core
  • AES core
    • Implemented according to the FIPS 197 documentation.
    • Also available in CBC, CFB and OFB modes.
    • Key size of 128, 192 and 256 bits.
    • Both encryption and decryption supported.
    Block Diagram -- AES core
  • SHA-1 Processor
    • Suitable for data authentication applications.
    • Fully synchronous design.
    • Available as fully functional and synthesizable VHDL or Verilog soft-core.
    • Xilinx and Altera netlist available for various devices.
    Block Diagram -- SHA-1 Processor
  • MD5 Processor
    • RFC 1321 compliant.
    • Suitable for data authentication applications.
    • Fully synchronous design.
    • Available as fully functional and synthesizable VHDL or Verilog soft-core.
    Block Diagram -- MD5 Processor
  • Triple DES core
    • Implemented according to the X9.52 standard
    • Implementation based on NIST certified DES core
    • Also available in CBC, CFB and OFB modes.
    • 112 or 168 bits keys supported.
    Block Diagram -- Triple DES core
  • SHA-256 Processor
    • This core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
    • The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.
    Block Diagram -- SHA-256 Processor
  • SNOW3G Stream Cipher Core
    • The Helion SNOW3G core efficiently implements the stream cipher used as the basis for the UEA2 confidentiality algorithm and UIA2 integrity algorithm which provide data security within the 3GPP UMTS and LTE mobile communication standards.
    • The core also fully supports the 128-EEA1 confidentiality and 128-EIA1 integrity algorithms which were introduced in 3GPP Specification Release 8, and which are identical to UEA2 and UIA2 respectively.
    Block Diagram -- SNOW3G Stream Cipher Core
×
Semiconductor IP