Cryptography IP

Compare 331 Cryptography IP from 61 vendors (1 - 10)

SHA-3 Crypto Core
- SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach.
- The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard.
- A common core is available for diverse ASIC & FPGA applications.
SM4-XTS Multi-Booster
- ASIC and FPGA
- High throughput
- Scalable solution
ARIA Crypto Engine
- Supports a wide selection of programmable ciphering modes
- Supports encryption & decryption
- Supports 128-bit, 192-bit & 256-bit key sizes
Chacha20-Poly1305 Multi-Booster - 800Gbps
- Fully compliant with RFC7539
- Supports encryption/decryption only (Chacha20)
- Supports authentication only (Poly1305)
SM4 Crypto Engine
- Supports encryption & decryption
- Performs key expansion
- Compliant with GBT.32907-2016
AES-GCM Multi-Booster
- High throughput
- Guaranteed performance with small packets
- 128-bit and 256-bit key
ChaCha20-Poly1305 Crypto Engine
- Fully compliant with RFC7539
- Supports encryption/decryption only (Chacha20)
- Supports authentication only (Poly1305)
Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
SHA-3 Crypto Engine
- FIPS 202 and FOS 180-4 compliant
- SHA3-224, SHA3-256, SHA3-384, SHA3-512
- SHAKE-128, SHAKE-256
3GPP Kasumi Accelerators
- Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
- Includes key scheduling hardware.
- Modes Kasumi
- Algorithms f8 and f9.
- Fully synchronous design.
- Low Speed, High Speed versions.