PCI IP
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PCI IP
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PCIe Gen 7 Verification IP
- The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interface of an IP or SoC.
- The PCIe Gen 7 VIP is fully compliant with latest PCI Express Gen 7 specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
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PCIe Switch Verification IP
- Compliant with the PCIe 6,5,4,3 specification.
- Support Pipe Specification 6.1.1
- NVMe on top of Low Power, CXS, CPI, CXL, CXL Security, PCIe Gen6/5/4/3 management
- Supports Pipe Specification 6.1 with both Low Pin Count and Serdes Architecture.
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PCIe Gen 6 Verification IP
- Compliant with PCI Express Specifications 6.1 (64GT/s), 5.0 (32GT/s), 4.0 (16GT/s), 3.1 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
- Support for 64.0 GT/s Data Rate per lane with backwards compatible.
- Support for new PAM4 Signalling and Gray Coding.
- Support for both Flit Mode & Non-Flit Mode.
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PCIe Gen 5 Verification IP
- Support for 32.0 GT/s Data Rate per lane with backwards compatible.
- Optimizing the Link to skip equalization at lower Data Rates when supporting 32.0 GT/s(optional feature).
- Lower pin count in pipe interface when supporting 32.0 GT/s.
- Support for newly added phy serdes architecture in pipe specification 5.0 .
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PCIe Gen 2 Verification IP
- Compliant with PCI Express Specifications 2.0 (5GT/s) and 1.1 (2.5GT/s).
- Verification IP configurable as PCI express Root Complex and Device Endpoint.
- Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
- Configurable pipe width : 8,16,32,64
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PCIe Gen 6 Phy
- Architecture optimized for HPC, AI/ML, storage, and networking
- Ultra-long reach, low latency, and low power
- Advanced DSP delivers unmatched performance and reliability
- PCIe Gen 6 Phy IPPCIe Gen 6 Phy IPComprehensive real-time diagnostic, monitor, and test features
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PCIe Gen 6 controller IP
- Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
- Supports SerDes Architecture PIPE 10b/20b/40b/80b width
- Supports original PIPE 8b/16b/32b/64b/128b width
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PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
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PCI v2.1 Master/Slave controller
- The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
- It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
- The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
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PCI v2.1 Host Controller
- The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
- PCI Host Bridge contains an internal arbiter to manage up to 4 external devices