PCI IP

Compare 551 PCI IP from 53 vendors (1 - 10)

PCIe Controller
- Implements PCIe 6.0 Specification at 64 GT/s
- Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
- Designed for easy integration with Alphawave PipeCORE™ PCIe PHY IP
- Key IP features configurable to optimize IP for exact application requirements
1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- The PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s).
- It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.
PCIe End Point IP Core
- The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0.
- The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics.
ULL PCIe DMA Controller
- The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
- With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.
PowerPC to PCI Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Supports all PowerPC CPU with 603 bus interface and MPC860 interface.
PCI Bus Arbiter
- Compliant with PCI bus specification 2.2.
- Designed for ASIC and PLD implementations in various system environments.
- Fully static design with edge triggered flip-flops.
- Supports two to eight bus masters.
PCI-ISA Bridge
- Compliant with PCI bus specification 2.1 and 2.2.
- Convert PCI transaction to ISA bus transaction.
- Function as PCI target on PCI bus.
- Function as ISA master on ISA bus.
PCI-to-PCI Bridge
- Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Independent asynchronous PCI clocks on primary and secondary bus.
AMBA AHB to PCI Host Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Supports AHB bus protocol.
- Downstream access transfer from AHB bus to PCI bus.
- Upstream access transfer from PCI bus to AHB bus.
64-bit PCI Host Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Designed for ASIC and PLD implementations.
- Supports both 64-bit and 32-bit bus systems.
- Fully static design with edge triggered flip-flops.