PCI IP
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PCI IP
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PCIe 6.0 / CXL 3.0 PHY & Controller
- Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
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PCIe 5.0/4.0/3.0 PHY & Controller
- Innosilicon’s PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, storage networks, automotive, and I/O connectivity applications
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PCIe GEN6 PHY IP
- The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
- It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
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FPGA Proven PCIe Gen6 Controller IP
- Supports up to x16 link width
- Support for Tx/Rx cut-through
- Supports 32 GT/s and 64 GT/s precoding
- Supports 14-bit tags for TLPs (Transaction Layer Packets)
- Supports buffering and credit management
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PCIe Switch for USB4
- Fully transparent design eliminates the need for Host configuration and management software
- Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
- Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
- Lowest latency switching logic on the market (2 clock cycles)
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PCIe Controller for USB4 with AXI
- Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link max. speed and width for reduced gate count and optimal throughput
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code – Gen5 support pending
- Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
- Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
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PCIe Controller for USB4
- Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
- Ultra-low Transmit and Receive latency (excl. PHY)
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PCIe 7.0 Switch
- Configurable from PCIe 7.0 x8/ PCIe6x16 @1GHz clock down to PCIe 5.0 x1
- Highly scalable with up to 31 configurable external or embedded endpoints
- Configurable Egress Buffer for non-blocking output queueing switch performance
- Flit mode to non-Flit mode conversion
- Low power optimized
- Superior performance through a nonblocking architecture
- Minimized footprint
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PCIe 7.0 Retimer Controller with CXL Support
- Supports PCIe 7.0 128 GT/s speeds at up to x16 lanes
- CXL 3.0 aware
- Supports PIPE 6.2.1 compatible PHYs
- Optimized for low latency
- Highly-configurable equalization algorithms and adaptive behaviors
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation