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IP for TSMC

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Compare 4,261 IP for TSMC from 107 vendors (1 - 10)
  • ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
    • Support ONFi 4.0 IO Electrical Specification
    • Support Legacy up to 50MHz
    • Support NV-DDR2 with operating frequency up to 533Mbps
    • Support NV-DDR3 with operating frequency up to 800Mbps
    Block Diagram -- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • JPEG encoder
    • Baseline JPEG compliant (ITU T.81), Motion JPEG
    • Up to 12 bits depth possible (default: 8 bit)
    • Super low latency (less than 1/10 of frame duration for rolling shutter cameras)
    • Lossy compression by default
    • Fully bit and cycle accurate co-simulation model available in Docker container
    Block Diagram -- JPEG encoder
  • Ku-Band Phased Array Tx-FE in TSMC 180nm RF
    • The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
    • It integrates X+Y transmitter channels on the same die and its low power makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
    Block Diagram -- Ku-Band Phased Array Tx-FE in TSMC 180nm RF
  • Ku-Band Phased Array Rx-FE in TSMC 180nm RF
    • The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
    • It integrates X+Y receiver channels on the same die and its low noise figure and wide baseband bandwidth makes it especially suitable for use in high-throughput modular digital Phased-Array Antenna products for mobile/tethered satellite communication applications.
    Block Diagram -- Ku-Band Phased Array Rx-FE in TSMC 180nm RF
  • 12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
    • The TRV101TSM40LP IP is a 1.1V low-power low-silicon-area 12-bit 80MHz Asynchronous-SAR ADC implemented in TSMC Low-Power 40nm CMOS process technology.
    • Its 40MHz Nyquist bandwidth makes it especially suitable for use in carrier-aggregated wireless communication integrated circuit subsystems (LTE, WiFi, WiMAX etc).
    Block Diagram -- 12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
  • Ultra-Low-Latency 10GE PHY+MAC
    • Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit 
    • Reconciliation sub-layer implementation compliant with IEEE802.3 
    • Local fault and remote fault detection and handling 
    • Frame Check Sequence (FCS) insertion and verification at line rate 
    Block Diagram -- Ultra-Low-Latency 10GE PHY+MAC
  • Ultra Low Latency 10G TCP Endpoint
    • The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
    • It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.
    Block Diagram -- Ultra Low Latency 10G TCP Endpoint
  • Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
    • The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.
    Block Diagram -- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY
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