IP for TSMC

Compare 4,332 IP for TSMC from 112 vendors (1 - 10)

PVT Sensor on TSMC CLN2P
Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
18-40MHz Crystal Oscillator on TSMC CLN2P
- Crystal Oscillator pad macro that supports industry standard crystals
- Uses standard CMOS transistors
- Crystal Oscillation Mode: Fundamental
- Power down option for IDDQ testing
PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
PCI v2.1 Host Controller
- The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
- PCI Host Bridge contains an internal arbiter to manage up to 4 external devices
PCI v2.1 Master/Slave controller
- The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
- It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
- The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
3GPP Kasumi Accelerators
- Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
- Includes key scheduling hardware.
- Modes Kasumi
- Algorithms f8 and f9.
- Fully synchronous design.
- Low Speed, High Speed versions.
802.11i CCMP/TKIP IP Core
- Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication with the CCMP protocol and RC4/”Michael” cipher for the TKIP.
- The WPA3 core is tuned for high data rate 802.11i applications (up to 2 Gbps for the CCMP protocol for 802.11n/802.11ac).
Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available