IP for TSMC

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Compare 4,288 IP for TSMC from 108 vendors (1 - 10)
  • 1G/2.5G/5G/10G/25G/50G MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 1G/2.5G/5G/10G/25G/50G MACsec
  • 10M MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very low-speed Ethernet used in automotive, industrial, and consumer applications.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and is optimized for the smallest area size.
    Block Diagram -- 10M MACsec
  • 100G / 200G / 400G / 800G / 1.6T MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 100G / 200G / 400G / 800G / 1.6T MACsec
  • Customizable Video Input controller
    • CVI is a fully Customizable Video Input controller IP core.
    • The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
    Block Diagram -- Customizable Video Input controller
  • Customizable Display Controller IP
    • CDC is a fully Customizable Display Controller IP supporting up to 16k resolutions (4096x4096 pixel) on a MIPI-DPI compliant parallel video output.
    • Several features can be configured at synthesis time and programmed at run time.
    • The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
    Block Diagram -- Customizable Display Controller IP
  • OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
    • D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores.
    • It is the first IP to bring 3D graphics OpenGL ES 2.0 rendering (with some ES 3.0 / 3.1 extensions) to the FPGA and SoC world and – with offline-shader compilers – even into MCUs or low-end MPUs with small amounts of memory and bare-metal or RTOS operation systems.
    Block Diagram -- OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
  • 3D OpenGL ES 1.1 GPU IP core
    • D/AVE 3D is cost-efficient IP core for 3D graphics applications.
    • This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software.
    Block Diagram -- 3D OpenGL ES 1.1  GPU IP core
  • 2.5D GPU
    • The D/AVE HD 2.5D GPU family is an evolution of the D/AVE 2D family supporting high quality 2D and 3D rendering for displays up to 4K x 4K.
    • Targeting modern graphics applications on high resolution displays in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets, the D/AVE HD fixed-function 2.5D GPU core is designed to be fast with powerful functionality.
    Block Diagram -- 2.5D GPU
  • Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
  • DDR3 and DDR4 Controller and PHY on TSMC 12nm
    • This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
    • Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
    Block Diagram -- DDR3 and DDR4 Controller and PHY on TSMC 12nm
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Semiconductor IP