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IP for TSMC

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Compare 4,426 IP for TSMC from 114 vendors (1 - 10)
  • Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles
    • Compliant with Bluetooth Low Energy specifications up to version 5.4
    • Supports all mandatory and optional features of Bluetooth low energy
    Block Diagram -- Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles
  • TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
    • Supports DDR5
    • DFI 5.1 compliant
    • Supports x4, x8 and x16 DRAMs
    • Up to 72 bits wide and up to 4 ranks
    Block Diagram -- TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
  • General-purpose & Specialized Ring PLLs + RTL-based Solutions
    • Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
    • Input & output frequency ranges greater than 1000:1
    Block Diagram -- General-purpose & Specialized Ring PLLs + RTL-based Solutions
  • LPDDR5X DDR Memory Controller
    • JEDEC LPDDR5X/LPDDR5 devices compatible
    • Data rates up to 8533Mbps
    • Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
    Block Diagram -- LPDDR5X DDR Memory Controller
  • MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
    • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
    • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
    Block Diagram -- MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
  • 800G Multi-Channel MACsec Engine with TDM Interface
    • Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
    • All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
    Block Diagram -- 800G Multi-Channel MACsec Engine with TDM Interface
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
    • 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
    Block Diagram -- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
  • MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
    • Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    Block Diagram -- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
  • Multiprotocol SerDes PMA
    • Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
    • Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
    • Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
    • Core-voltage line driver with programmable pre-and post-emphasis
    Block Diagram -- Multiprotocol SerDes PMA
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