HDLC IP
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9
HDLC IP
from 7 vendors
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9)
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High-Level Data Link Controller
- Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Primary Rate) unit.
- These single channel HDLC controllers handle all interframe flags, delimiting flags and Frame Check Sequence (FCS) pattern.
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HDLC & SDLC Protocol Controller
- The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols.
- It is based on the Intel® 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.
- The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors.
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Used for controlling HDLC/SDLC transmission protocols
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
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Single Channel HDLC Controller
- Single port synchronous serial line interface.
- Flag/Abort Generation/Detection.
- Zero Insertion/Deletion.
- Non-octet alignment detection.
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Enhanced Multiprotocol Serial Communication Controller
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
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HDLC Framer
- Best-in-Class size and performance, supports many thousands of channels.
- Supports bit-synchronous and byte-synchronous HDLC.
- Generates/Accepts data for multiple independent TDM HDLC streams. Generates/Removes flag characters to delineate HDLC frames.
- Inserts/Removes HDLC bit or byte stuffing. Provides variable width data output.
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HDLC/SDLC controller
- Two separate receiver and transmitter interfaces.
- Two separate, configurable FIFO buffers for receiver and transmitter
- Bit stuffing and unstuffing
- Address recognition for receiver and address insertion for transmitter
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FPGA Dual HDLC Serial Port
- General Features:
- HDLC Features:
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Async/HDLC Serial Channel
- Async mode with optional address and parity bit
- HDLC mode with Flag generation, CRC and Abort capability
- Digital PLL and data encode/decode
- Four bytes of buffering for both receive and transmit