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Quad SPI Controller
- Configurable SPI modes
- Supports programmable SPI clocking modes
- Programmable interrupt on SPI-done
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Path tracing/Ray tracing accelerator
- Powerful Path Tracing Acceleration GPU IP Solution
- ‘Unified’ Traversal and Intersection Test
- Based on High Performance MIMD Architecture
- Highly Applicable for Servers and High End GPU Chips
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Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
- parameterized search-window size
- parameterized number of bits per pixel
- efficient implementation
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AXI Fabric Package for Scalable SoC Applications
- AE300FB – AXI Fabric
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0.035... 100 MHz intermediate-frequency amplifier
- TSMC 65 nm CRN65LP technology
- Differential inputs, outputs
- High frequency 0.035 – 100 MHz
- High linearity
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HDLC frame to APB bridge
- HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .
- The module is accessed through an APB slave from the host side.
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SPI - Verifies reliable data transfer and protocol compliance in SPI systems
- SPI (Serial Peripheral Interface) is a high-speed, synchronous communication protocol that ensures reliable data transfer between microcontrollers and peripherals. It verifies correct data transmission, signal timing, and error handling in SoC designs.
- This versatile Verification IP (VIP) supports various SPI modes and clock configurations, enabling robust testing of master-slave communication, data integrity, and error conditions across multiple applications in embedded systems, automotive, IoT, and more
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SPI Flash Controller - Ensures reliable validation of SPI Flash memory controllers
- The SPI Flash Controller Verification IP (VIP) is a powerful tool for verifying and simulating SPI Flash memory controllers in SoCs. It supports single, dual, and quad SPI modes, enabling seamless validation of read, write, erase, and advanced operations.
- This VIP is designed for diverse applications, including IoT devices, automotive systems, consumer electronics, and aerospace. It ensures efficient performance, low power usage, and reliable integration of SPI Flash memory in mission-critical and everyday devices
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Scatter Gather DMA Engine - Validates efficient scatter-gather DMA for high-performance data transfer
- The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather DMA controllers in SoCs. It ensures efficient data transfer between non-contiguous memory regions while minimizing CPU utilization, offering features like protocol compliance and transaction monitoring.
- Ideal for applications such as networking, multimedia, storage, and embedded systems, the VIP helps ensure high-performance, reliable data movement. It supports multi-channel configurations, error injection, and performance monitoring to optimize system efficiency and robustness
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Simulation VIP for SPDIF
- Maximum Audio Sample Word Length
- Supports both 20-bit and 24-bit audio word length format. In 20-bit audio word length format, AUX field will be present
- Audio Sample Word Length
- Supports padding in audio data if audio sample word length is less than the maximum audio word length
