Other

The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance
It is used to connect peripherals around the CPU and to replace the Industry Standard Architecture (ISA) bus which can only run up to 8 MHz
The primary benefit is that signals can be transmitted across a minimum of seven traces for an LPC bus versus 52 traces for an ISA bus
This relieves the pressure of routing on the often-congested motherboard and at the same time improves the overall system integrity

SPI (Serial Peripheral Interface) is a high-speed, synchronous communication protocol that ensures reliable data transfer between microcontrollers and peripherals. It verifies correct data transmission, signal timing, and error handling in SoC designs.
This versatile Verification IP (VIP) supports various SPI modes and clock configurations, enabling robust testing of master-slave communication, data integrity, and error conditions across multiple applications in embedded systems, automotive, IoT, and more

The SPI Flash Controller Verification IP (VIP) is a powerful tool for verifying and simulating SPI Flash memory controllers in SoCs. It supports single, dual, and quad SPI modes, enabling seamless validation of read, write, erase, and advanced operations.
This VIP is designed for diverse applications, including IoT devices, automotive systems, consumer electronics, and aerospace. It ensures efficient performance, low power usage, and reliable integration of SPI Flash memory in mission-critical and everyday devices

The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather DMA controllers in SoCs. It ensures efficient data transfer between non-contiguous memory regions while minimizing CPU utilization, offering features like protocol compliance and transaction monitoring.
Ideal for applications such as networking, multimedia, storage, and embedded systems, the VIP helps ensure high-performance, reliable data movement. It supports multi-channel configurations, error injection, and performance monitoring to optimize system efficiency and robustness

The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite.
The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy.

The MTS-E core multiplexes and encapsulates audio, video, and metadata streams in a single MPEG Transport Stream (MTS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets.
Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video.

Maximum Audio Sample Word Length
Supports both 20-bit and 24-bit audio word length format. In 20-bit audio word length format, AUX field will be present
Audio Sample Word Length
Supports padding in audio data if audio sample word length is less than the maximum audio word length