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Compare 313 Other from 34 vendors (1 - 10)
  • 8b/10b Encoder/Decoder
    • The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applications.
    • The design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices.
    Block Diagram -- 8b/10b Encoder/Decoder
  • Register, Configuration and Control Bus
    • A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc..
    • The bus is especially suited for synthesizable designs. It is specifically developed to meet the challenges of long interconnect delays in large System-on-chip designs and can be tailored to match system clock rates.
    Block Diagram -- Register, Configuration and Control Bus
  • ST2059-1&2 IP
    • This IP generates a timing signal standardized in SMPTE ST 2059 using IEEE1588v2 Precision Time Protocol (PTP).
    • The timing signal is utilized as “GenLock” signal which has been used in conventional A/V system.
    Block Diagram -- ST2059-1&2 IP
  • MECHATROLINK-III Master/Slave IP
    • Functionally compatible with JL-100 which is the ASIC for MECHATROLINK-III Master/Slave communication.
    • Parameters required for MECHATROLINK-III communication are set either by cpu or through external pins.
    Block Diagram -- MECHATROLINK-III Master/Slave IP
  • Multichannel DMA Intel FPGA IP for PCI Express*
    • The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
    • With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.
    Block Diagram -- Multichannel DMA Intel FPGA IP for PCI Express*
  • OCP Verification IP
    • Compliant with OCP 3.1 specification.
    • Supports OCP Master, OCP Slave, OCP Monitor and OCP Checker.
    • Supports all OCP protocol transfer & command types.
    • Supports all OCP protocol signal widths including address and data.
    Block Diagram -- OCP Verification IP
  • Low Pin Count (LPC) controller verification IP
    • The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance
    • It is used to connect peripherals around the CPU and to replace the Industry Standard Architecture (ISA) bus which can only run up to 8 MHz
    • The primary benefit is that signals can be transmitted across a minimum of seven traces for an LPC bus versus 52 traces for an ISA bus
    • This relieves the pressure of routing on the often-congested motherboard and at the same time improves the overall system integrity
    Block Diagram -- Low Pin Count (LPC) controller verification IP
  • Quad SPI Controller
    • Configurable SPI modes
    • Supports programmable SPI clocking modes
    • Programmable interrupt on SPI-done
    Block Diagram -- Quad SPI Controller
  • HDLC frame to APB bridge
    • HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .
    • The module is accessed through an APB slave from the host side.
    Block Diagram -- HDLC frame to APB bridge
  • SPI - Verifies reliable data transfer and protocol compliance in SPI systems
    • SPI (Serial Peripheral Interface) is a high-speed, synchronous communication protocol that ensures reliable data transfer between microcontrollers and peripherals. It verifies correct data transmission, signal timing, and error handling in SoC designs.
    • This versatile Verification IP (VIP) supports various SPI modes and clock configurations, enabling robust testing of master-slave communication, data integrity, and error conditions across multiple applications in embedded systems, automotive, IoT, and more
    Block Diagram -- SPI - Verifies reliable data transfer and protocol compliance in SPI systems
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