Embedded Memories IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.

Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB

The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
The interface signals are fully synchronous; no asynchronous signals are present on either side.
Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.

The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
Only single control lines are re-synchronized between the two clock domains ensuring hazard free operation.
The requirement for Gray coded addressing is thus eliminated. A wide range of clock frequencies and relative frequencies between read and write ports are fully tolerated.

Weebit Resistive RAM (ReRAM) is a new type of Non-Volatile Memory (NVM) that is designed to be the successor to flash memory.
Weebit ReRAM IP can provide a high level of differentiation for System-on-Chip (SoC) designs, with performance, power, cost, security, environmental, and a range of additional advantages compared to flash and other NVMs.
Weebit’s first ReRAM IP product is available now in SkyWater Technology’s 130nm CMOS process (S130). The technology is fully qualified, available for integration in SkyWater’s users’ SoCs, and ready for production.