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Hardware Security Module
- GRHSM is an isolated system-on-chip (SoC) that can be used as a subsystem in a larger SoC design to implement a hardware security module or otherwise provide security functions to the larger system.
- Use cases include crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.
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LZRW3 Data Compression Core
- The Helion LZRW3 core implements the LZRW3 data compression algorithm in Altera FPGA without the need for external memory storage.
- It is capable of handling data throughputs in excess of 1 Gigabit/sec, and is ideal for use for improving system performance and efficiency in data communications, networking and data storage applications.
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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Hardware Security Module (HSM) for Automotive
- Secure key provisioning
- Secure key storage
- Secure counter
- Flexible anti-tampering
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Intrusion Detection System (IDS)
- Part of a global threat detection, analysis and response solution form Chip-to-Cloud relying on Securyzr™ iSSP (integrated Security Services Platform).
- Compliance with standard and Regulation.
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nQrux™ Confidential Computing Engine (CCE)
- Complete physical isolation of code & data
- Secure code & data transmission with TLS 1.3 Quantum-safe crypto option
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Anti-Counterfeiting Digital IP - Self-aware and Anti-bypass
- Texplained’s countermeasure is schematically composed of two main blocs:
- 1. The Detection Module detects the attack « on the fly »
- => Its checks the execution flow of the software to detect if a Hardware attack is in progress
- 2. The Defense Module reacts to the attack by preventing the striker to obtain the code in the NVW
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FPGA Lock IP
- The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin to lock down FPGAs and hardwareto stop IP theft and prevent CEM hardware counterfeiting.
- It can also be used to guarantee hardware integrity in Military/Defence or Medical applications.
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CPU-less TLS1.3 Offload IP core for FPGA Acceleration
- TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required.
- Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now
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Cutting-Edge Hardware Security IP
- The IoT’s hardware security IP, provides SoC manufacturers with robust, modular, and advanced security and cryptographic capabilities.
- The solutions address IoT security requirements, with upgradable cryptographic capabilities to adapt to evolving conditions.
- The KSE Portfolio provides a diverse range of proven, certification-ready embedded security features, compliant with key governmental and industry standards.
