USB IP

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Compare 742 USB IP from 50 vendors (1 - 10)
  • USB3.2 PHY & Controller
    • USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications
    • Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals
    • In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers
    Block Diagram -- USB3.2 PHY & Controller
  • USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
    • USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications
    • Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals
    • In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers
    Block Diagram -- USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
  • USB4 VIP
    • The USB4 Verification IP (MX_USB4_VIP) provides a highly capable verification solution for the USB4 protocol which incorporating bus functional model (BFM), integrated protocol checkers and functional coverage along with assertion check
    • The USB4 VIP can be readily customized and optimized for a wide range of specific system application
    Block Diagram -- USB4 VIP
  • USB 1.1 Host Controller IP
    • The USB Host, as defined by the OHCI specification, is a hardware controller designed to manage communication between a host system and USB 1.1 devices.
    • It supports Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates and handles all four USB transfer types: Control, Bulk, Interrupt, and Isochronous.
    Block Diagram -- USB 1.1 Host Controller IP
  • PCIe Switch for USB4
    • Fully transparent design eliminates the need for Host configuration and management software
    • Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
    • Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
    • Lowest latency switching logic on the market (2 clock cycles)
    Block Diagram -- PCIe Switch for USB4
  • USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
    • XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification. It supports SuperSpeed+ data rates up to 20 Gbps, ensuring protocol compliance, power management, and seamless interoperability across versions.
    • The product’s advanced features include dynamic link negotiation validation, error injection, and robust debugging tools. It enables testing across a range of devices, ensuring high-speed data transfer and reliable performance in both legacy and modern USB designs
    Block Diagram -- USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
  • USB 4.0 - Enables fast data transfer, efficient power delivery, and connectivity
    • USB 4.0 is the third major revision of the USB standard, offering data transfer speeds up to 20 Gbps via dual-lane operation. It supports multiple transfer modes and improved bandwidth utilization for high-speed applications.
    • USB 4.0 enables seamless connectivity across various devices, from storage and printers to high-performance audio and video equipment. It enhances power delivery and ensures efficient data transfer for consumer electronics, networking, and industrial applications.
    Block Diagram -- USB 4.0 - Enables fast data transfer, efficient power delivery, and connectivity
  • USB3.1 transceiver IP with PMA and PCS layer
    • Data rate for Gen 1 physical layer is 5Gbps
    • Data rate for Gen 2 physical layer is 10Gbps
    • 4 Channel per Quad
    • Shared high performance LC tank PLL
    Block Diagram -- USB3.1 transceiver IP with PMA and PCS layer
  • USB 3.1 Cable Marker IP
    • The OTC9115 is a complete, low cost, single chip cable marker for USB PD Type-C (baseband) cables.
    • In low silicon area and just 4 IOs, the device has been designed exclusively for very high volume Type-C cables with basic marker requirements.
    Block Diagram -- USB 3.1 Cable Marker IP
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery  IP
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