The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The core includes a hardware floating point unit, L1 data & instruction caches, an L2 cache and an MMU. Tessent trace is available as an option.
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
Dual-issue Linux-capable RISC-V core
Overview
Key Features
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
- Dual-issue superscalar
- In-order 7-9 stage pipeline
- Interrupt controller options
- WFI
- NMI
- PLIC
- Dynamic jump prediction
- FPU
- L1 data and instruction caches
- L2 cache
- MMU
- On-chip debugger
- Optional trace
Benefits
- Standards compliance
- RISC-V RVA22 profile
- Code density
- Zc extensions
- High configurability with Codasip Studio
Block Diagram
Applications
- Communications
- Industrial electronics
- Automotive
- Consumer electronics
- Wearables
- Advanced cameras
Deliverables
- Hardware development kit (HDK)
- Human-readable System Verilog RTL
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- GCC C-compiler
- Assembler
- Disassembler
- Linker
- Instruction-accurate simulator
- Cycle-accurate simulator
- Profiler
- Options for configuring A730
- CodAL model for Codasip Studio
- Full-feature Studio tool for configuring A730 core
Technical Specifications
Availability
Contact us
Related IPs
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- Ultra Compact 32-bit RISC-V CPU Core
- 64-bit RISC-V Multi-Core Linux-Capable processor
- 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA
- 32 bit - Compact RISC-V Processor Core
- 32 Bit - Embedded RISC-V Processor Core