AMBA AHB / APB/ AXI IP

Compare 334 AMBA AHB / APB/ AXI IP from 38 vendors (1 - 10)

SPI to AHB Bridge
- The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
- On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
- The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.
10/100 Mbit Ethernet MAC
- The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
- The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
CAN 2.0 Controller with DMA
- GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.
- The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.
AMBA AHB Direct Memory Acess (DMA) Controller
- Multiple independent DMA channels with direct AHB bus interface.
- DMA transfers between AHB memory devices and I/O ports.
- Scatter-gather allows DMA to merge multiple data source to contiguous space.
- Supports both hardware initiated transfer and software initiated transfer.
AMBA AHB Bus Master
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to any slave devices on the AHB Bus.
- User specified single or burst data access on the AHB interface and user interface.
- Handles wait state insertion by any slave devices.
AMBA AHB Bus Slave
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to two sets of on-chip or off-chip modules.
- Four write buffers to process posted write.
- Dual read buffers to process CPU read.
AMBA AHB to PCI Host Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Supports AHB bus protocol.
- Downstream access transfer from AHB bus to PCI bus.
- Upstream access transfer from PCI bus to AHB bus.
AMBA AXI5 Verification IP
- AXI5 VIP is Compliant with the latest ARM™ AMBA AXI5 & AXI5 lite.
- It is also compatible with AXI3, AXI4 Protocol Specification v2.0 referred to as AXI4 and AXI4-Lite.
- Supports Unique ID feature for both read and write transactions.
- Supports MTE(Memory Tagging Extension) feature to detect memory safety violations.
AMBA AXI4 Verification IP
- Compliant to AMBA® AXI4 specifications from ARM and
- supports for all variants of AXI4, AXI4-Lite and AXI4 Stream.
- Support for all type of AMBA AXI4 devices.
- Strong protocol checking Bus Monitor which also provides statistics of the transactions.
AMBA AXI STREAM Verification IP
- Compliant with AMBA® AXI5- Stream and AXI4-Stream.
- Support for all types of AMBA AXI5-Stream and AXI4-STREAM components.
- Supports parameterized data widths.
- Supports byte stream transmission number of data and null bytes.