DPA and FIA Countermeasures IP

The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin to lock down FPGAs and hardwareto stop IP theft and prevent CEM hardware counterfeiting.

• 1. AMBA-AXI-4.0 Master and Slave
• 2. Blocks user to snoop the meaningful data.
• 3. Block User from SPA/ DPA Gassing the secure data.
• 4. End to End ECC Secured transactions.

• 1. AMBA-AHB Master and Slave
• 2. Blocks user to snoop the meaningful data.
• 3. Block User from SPA/ DPA Gassing the secure data.
• 4. End to End ECC Secured transactions.

• Adaptability for consumer requirements
• Product are customized based on customer requests
• Low latency
• Tunable in terms of:

• Accelerates AES according to FIPS-197 supporting all key sizes
• NIST SP 800-38A: Recommendation for Block Cipher Modes of Operation
• NIST SP 800-38B Block Cipher with Cipher-based Message Authentication Code (CMAC)
• NIST SP 800-38C Block Cipher with Counter with Cipher Block Chaining-Message Authentication Code (CCM)

• Texplained’s countermeasure is schematically composed of two main blocs:
• 1. The Detection Module detects the attack « on the fly »
• => Its checks the execution flow of the software to detect if a Hardware attack is in progress
• 2. The Defense Module reacts to the attack by preventing the striker to obtain the code in the NVW