IP for Samsung

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures.
With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification.
This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.

The Intra-panel TX PHY IP is an advanced chip-on-glass (ACOG) and chip-on-film (COF) transmitter embedded into the timing controller for TFT-LCD panels.
This technology enables a single chip to support multiple display interfaces, reducing system costs and complexity.
It also provides higher data transfer rates, lower power consumption, and compatibility with a wide range of devices.

The PCIe 5.0/6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 5.0/6.0 specification.
This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

The PCIe 4.0 PHY IP consists of hardmacro PMA and softmacro PCS compliant with PCIe Base 4.0 specification.
This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.

The MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included.
In addition, extensive built-in self-test features, such as loopback and scan, are supported.
It offers a cost-effective and low-power solution.

The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included.
In addition, extensive built-in self-test features, such as loopback and scan, are supported.
It offers a cost-effective and low power solution.

The MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included.
In addition, extensive built-in self-test features, such as loopback and scan, are supported.
It offers a cost-effective and low-power solution.