DSP Core IP

Compare 30 DSP Core IP from 16 vendors (1 - 10)

Audio and control DSP
- Quad 16x16 MACs
- Dual 32x32 MACs
- 4-way VLIW
Tensilica HiFi 1 DSP
- Cycle and energy efficient for Bluetooth and Bluetooth Low Energy (BLE) codecs for speech and music
- Efficient neural network acceleration ISA and architecture support
Tensilica Vision Q7 DSP
- Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
16 bit DSP fixed point coprocessor
- The APS DSP has been designed from the ground up as a companion to the APS family of processors, ensuring simple integration into your embedded system.
- The additional instructions are fully integrated with the assembler and simple macros make using the DSP from C or C++ very simple.
18-Bit Pipeline DSP Slice IP
- Timing resolution: 80ps
- Operating frequency range: 160MHz – 700 MHz
- Lock time: 11 cycles
- Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
Complex DSP Engine Core
- Consists of Conjugation unit, Complex Multiplier, Pre-adder and two Complex Accumulators (X and Y).
- Parameterizable input widths
- Parameterizable accumulator widths
- Full precision multiplier output available
Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- A comprehensive design environment and toolset
- Very fast work-flow through the use of high-level front-end hierarchical Graphical Programming Environment, Core Synthesis and back-end “Tuning” tools
Ultra low power C-programmable Baseband Signal Processor core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (65k gates), excluding debug interface (6k gates)
- Small memory footprint
Ultra low power C-programmable DSP core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (43k gates), excluding debug interface (6k gates)
- Small memory footprint
16-bit Fixed-Point DSP
- 16 bit fixed point customizable DSP
- Single cycle 16 bit signed/unsigned multiplier
- 1 or more 40bit accumulator(s)
- 64k X data, Y data and program memory range