IP for GLOBALFOUNDRIES

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Compare 1,103 IP for GLOBALFOUNDRIES from 61 vendors (1 - 10)
  • Ultra-short reach SerDes with 500 Gbit/s throughput
    • 2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
    • High pin-efficiency and low power
    • 208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)
    Block Diagram -- Ultra-short reach SerDes with 500 Gbit/s throughput
  • SATA II v2.6 Host Controller
    • The SATA II Host Controller implements an AHCI/Emulation interface that interfaces with SATA PHY using the SAPIS interface on one side and to an application on the other side using the VCI interface.
    • The emulation interface is used to be backward compatible with existing software and supports both PIO and DMA modes of operation.
    Block Diagram -- SATA II v2.6 Host Controller
  • SATA II v2.6 Device Controller
    • The SATA II Device Controller interfaces with SATA PHY using the SAPIS interface on one side and to an application on the other side using the VCI interface.
    • It supports PIO, DMA, QDMA, and FPDMA modes of operation and supports NCQ using the FPDMA mode of operation. It also supports SATA power management features
    Block Diagram -- SATA II v2.6 Device Controller
  • SATA PHY
    • Serial ATA II Revision 2.6 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    • Initialization and power saving modes
    Block Diagram -- SATA PHY
  • XAUI PHY
    • Very low output jitter
    • Receiver equalization for enhanced jitter tolerance
    • Programmable TX levels with multiple post-cursor emphasis options
    • Automatic driver/receiver impedance calibration
    Block Diagram -- XAUI PHY
  • PCIe Gen2 PHY
    • PCI Express Gen 2 and Gen 1 compliant
    • Supports various PCI Express modes and extensions
    • Programmable amplitude and pre-emphasis
    • Programmable receiver equalization
    Block Diagram -- PCIe Gen2 PHY
  • PCIe Gen3 PHY
    • Low Risk - Silicon proven with Si characterization data
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- PCIe Gen3 PHY
  • PCI v2.1 Host Controller
    • The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
    • PCI Host Bridge contains an internal arbiter to manage up to 4 external devices 
    Block Diagram -- PCI v2.1 Host Controller
  • PCI v2.1 Master/Slave controller
    • The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
    • It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
    • The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
    Block Diagram -- PCI v2.1 Master/Slave controller
  • 5V ESD Clamp in GlobalFoundries 180nm LPe
    • A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
    • A key attribute of this 5V Clamp is that it can be used for either signal protection or 1.8V power supplies.
    • The clamp is a single cell, 44um x 32um in size. It is built from the substrate to metal 6.
    Block Diagram -- 5V ESD Clamp in GlobalFoundries 180nm LPe
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