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VESA DSC IP

Welcome to the ultimate VESA DSC IP hub! Explore our vast directory of VESA DSC IP Cores

VESA DSC IP cores provide a low-latency, low-complexity codec specifically designed for data compression over the display interface.

VESA Display Compression Codecs (DSC) IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image.

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Compare 27 VESA DSC IP from 10 vendors (1 - 10)
  • Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
    • The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard.
    • It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits per component color depths.
    • The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.
    Block Diagram -- Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
  • Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
    • The UHT-DSC-E core is an advanced video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard.
    • It supports encoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits sample depths.
    • The core is scalable and has been designed for enabling ultra-high throughput video encoding, even in medium-range target implementation technologies.
    Block Diagram -- Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
  • DisplayPort 1.4 FEC Receiver (Rx)
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- DisplayPort 1.4 FEC Receiver (Rx)
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
  • DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    Block Diagram -- DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
  • VESA DSC Encoder
    • VESA Display Stream Compression (DSC) 1.2b compliant
    • Supports all DSC 1.2b mandatory encoding mechanisms: MMAP, BP, MPP, and ICH
    • Output buffering compatible with transport stream over video interfaces
    • Configurable maximum display resolution
    • Configurable compressed bit rate, in increments of 1/16 bpp
    • 8, 10, 12, 14, and 16 bits per video component
    • YCbCr and RGB video input format
    • 4:4:4, 4:2:2, and 4:2:0 native coding
    Block Diagram -- VESA DSC Encoder
  • VESA DSC Decoder
    • VESA Display Stream Compression (DSC) 1.2b compliant
    • Supports all DSC 1.2b mandatory encoding mechanisms: MMAP, BP, MPP, and ICH
    • Output buffering compatible with transport stream over video interfaces
    • Configurable maximum display resolution
    • Configurable compressed bit rate, in increments of 1/16 bpp
    • 8, 10, 12, 14, and 16 bits per video component
    Block Diagram -- VESA DSC Decoder
  • Simulation VIP for DSC
    • DisplayPort
    • DSC Version
    • DSC 1.2a (VBR is not supported by the DP specification)
    • Configuration
    Block Diagram -- Simulation VIP for DSC
  • VESA DSC Encoder IIP
    • Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
    • Full DSC Encoder functionality.
    • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    Block Diagram -- VESA DSC Encoder IIP
  • VESA DSC Decoder IIP
    • Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
    • Full DSC Decoder functionality.
    • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    Block Diagram -- VESA DSC Decoder IIP
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