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Audio Processor IP

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Audio processors have hardware architectures that are tailored for audio processing, reducing not just the power but also the overall silicon cost.

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Search (14)
Compare 14 Audio Processor IP from 6 vendors (1 - 10)
  • Neural-network-based noise cancellation
    • Enhanced speech intelligibility for voice-enabled devices
    • Significantly reduces barrier-to-entry for voice-enabled device makers
    Block Diagram -- Neural-network-based noise cancellation
  • Spatial Audio & Head Tracking Solution
    • Ceva-RealSpace is a complete Spatial Audio software solution combining precise 3D rendering and accurate, low-latency head tracking.
    • RealSpace supports multiple system architectures, giving you the flexibility to render content directly on TWS earbuds, headphones, XR headsets, or speakers for the lowest latency. Or choose to render on mobile phones, gaming systems, or PCs and save BOM costs on the device.
    • RealSpace operates independently of audio codec choices, source vendors, or device ecosystems. Pre-integrated on some of the top audio SoCs in the industry, Ceva-RealSpace helps you bring cutting-edge products to market faster and with less risk.
    Block Diagram -- Spatial Audio & Head Tracking Solution
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
  • ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
  • ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
  • ARC HS47Dx4 quad-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47Dx4 quad-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • ARC HS47Dx2 dual-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47Dx2 dual-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • Quad MAC DSP core
    • Four 16b macs/cycle or Two 32b macs/cycle
    • 8/16/32/64 data types
    • SIMD support
    • High precision (upto 72 bit accumulation)
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