Standard cell IP
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6 track High Density standard cell library at TSMC 180 nm
- Less Silicon
- High Density optimization
- 6-Track high cells for optimal area reduction
- Only Metal 1 used for cell design
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9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
- Easy creation of ultra low leakage islets: reduce leakage up to 1000 times at 180 nm
- Power-off or even avoid a regulator thanks to direct battery or pad interface
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6 track High Density standard cell library at TSMC 55 nm
- High Density optimization
- with island construction kit
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6 track High Density standard cell library at TSMC 55 nm
- High Density optimization
- with island construction kit
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9 track standard cell library at TSMC 55 nm
- Compromise for density and speed
- 9-Track high cells
- Only Metal 1 used for cell design
- Compatible with 1P3M SoC implementation
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9 track standard cell library at TSMC 55 nm
- Compromise for density and speed
- 9-Track high cells
- Only Metal 1 used for cell design
- Compatible with 1P3M SoC implementation
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7 track Extra Low Consumption standard cell library with Dual voltage capability
- Power consumption is divided by up to 5
- Standard cells optimized for low-power at the schematic level
- Battery life increases
- Decrease of heat and life stress of the circuit