CXL IP
Welcome to the ultimate CXL IP hub! Explore our vast directory of CXL IP
All offers in
CXL IP
Filter
Compare
36
CXL IP
from 14 vendors
(1
-
10)
-
PCIe 6.0 / CXL 3.0 PHY & Controller
- Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
-
CXL 3 Controller IP
- The CXL 3 Controller IP is designed to support dual-mode operation, allowing dynamic selection between host and device modes.
- It connects to standard 64GT/s PHYs through the PIPE 6.x interface and supports high data rates across various link widths.
-
CXL 3.1 Controller
- Ultra-low Transmit and Receive latency
- Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
- Supports backwards compatibility to PCIe 6.1
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
- Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
- Merged Replay and Transmit buffer enables lower memory footprint
-
CXL 2.0 Controller with AXI
- Supports the latest CXL specification
- AMBA AXI Layer for CXL.io
-
CXL 2.0 Controller
- Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
-
CXL - Enables robust testing of CXL-based systems for performance and reliability
- CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol. With features like protocol compliance checks, cache coherency validation, and advanced debugging tools, it ensures robust and efficient testing of high-performance computing systems.
- From HPC and AI to automotive and edge computing, CXL Verification IP supports diverse applications. It enables seamless communication between processors, memory, and accelerators, ensuring reliable performance in data centers, ML systems, cloud infrastructures, and telecom networks.
-
Simulation VIP for CXL
- Device Configuration
- Host, Device
- Spec Version
- 1.1, 2.0, 3.0
-
CXL Verification IP
- Supports CXL specs revision 1.0, 1,1 and 2.0.
- Supports Native PCIe mode and below features as defined in the PCIe specification.
- PCIE Express specs 1.0/2.0/3.0/4.0/5.0/5.1
- Serial, PIPE, PCS/PMA, Low pin count and SerDes interface
-
CXL CONTROLLER IIP
- Compliant with CXL 1.0/1.1 Specifications
- Supports Native PCIe mode and below features as defined in the PCIe specification
- PCIE Express specs 1.0/2.0/3.0/4.0/5.0
- PIPE interface
-
CXL Switch Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support