SPI IP

This Universal NOR Flash IP supports a variety of NOR Devices and multiple Protocols, combines ease of use with high reliability, low power and speed under all conditions, including automotive applications.

The xSPI master IP supports the xSPI JESD251 standard from a standard AXI4 slave interface, and also features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces. Also supports JEDEC SFDP Standard.

• The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs. When coupled with the ACS xSPI PHY, the combined IPs are able to interact with SPI, Dual SPI, Quad SPI, Octal SPI, and xSPI devices at the full 200 MHz data rate.
• This includes both HyperRAM and HyperFlash protocols. Both single and dual data rate modes are supported. The xSPI Master controller IP supports flash devices, whereas the xSPI/PSRAM controller has been designed to support SRAM types of devices using the same interface.

• The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
• On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
• The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.

• The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
• Through registers mapped into APB address space the core can be configured to work either as a master or a slave.

• The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suitable for use in sensitive applications.
• Error detection through the SPI is crucial in ensuring the safety and reliability of airplanes.
• The SafeSPI protocol ensures that all data transfer is performed securely, preventing any unauthorized access to the transmitted data.

• The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - performance applications that require fast data transfer rates.

• The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
• The Serial Peripheral Interface (SPI)  bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.

• The SPI Slave IP Core implements an SPI Slave fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
• The Serial Peripheral Interface (SPI)  bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.

• The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
• It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices

• The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices