SPI IP
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83
SPI IP
from 23 vendors
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SPI to AHB Bridge
- The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
- On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
- The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.
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SPI Controller
- The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
- Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
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SafeSPI - Function Controller
- The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suitable for use in sensitive applications.
- Error detection through the SPI is crucial in ensuring the safety and reliability of airplanes.
- The SafeSPI protocol ensures that all data transfer is performed securely, preventing any unauthorized access to the transmitted data.
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SPI - Function Controller
- The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - performance applications that require fast data transfer rates.
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SPI Master DO-254 IP Core
- The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
- The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.
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SPI Slave DO-254 IP Core
- The SPI Slave IP Core implements an SPI Slave fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
- The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.
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Expanded Serial Peripheral Interface (xSPI) Slave Controller
- The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
- It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
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Expanded Serial Peripheral Interface (xSPI)Master Controller
- The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
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SPI/BOSCH Verification IP
- Follows SERIAL_FLASH basic specification as defined in Bosch SMB380 Triaxial acceleration sensor
- Support Master and Slave Mode
- Supports data width of 8 bit
- Supports 3-wire,4-wire interface
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SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfers (both Full Duplex and Half Duplex) to/from a AMBA APB, AXI, or AHB Interconnect.
- The DB-SPI-S-AMBA-BRIDGE contains dual clock Transmit/Receive FIFOs and Finite State Machine control to process incoming SPI transmit/receive transactions, and a AMBA Master Interface (i.e. APB, AXI, AHB5) to read or write the SPI payload data with respect to the AMBA Interconnect. No processor is required for configuration or control; the DB-SPI-S-AMBA-BRIDGE operates autonomously from reset.
