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Interrupt Controller IP

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Compare 14 Interrupt Controller IP from 10 vendors (1 - 10)
  • SDIO/SD Memory/MMC Slave Controller
    • Compatible with SD/SDIO specification 2.0 with 1 and 4 bit data transfer.
    • Provides SD interface to peripheral or memory device through a simple address/data interface.
    • Support SD, SPI and optional MMC bus protocol.
    • Support for both standard capacity and high capacity (SDHC) memory cards.
    Block Diagram -- SDIO/SD Memory/MMC Slave Controller
  • APB Interrupt Controller
    • The interrupt controller monitors interrupts from all other modules within the system and issues interrupt requests to the processor when necessary.
    • The interrupt controller is scalable to support from 1 to 32 interrupt sources. It also provides enable set and enable clear mechanisms to prevent dangerous read-modify-write operations.
    Block Diagram -- APB Interrupt Controller
  • Intel 8259A Functional Equivalent Programmable Interrupt Controller
    • MCS-80/85 and 8088/8086 processor modes.
    • Fully Nested Mode and Special Fully Nested Mode.
    • Special Mask Mode.
    • Buffered Mode.
    Block Diagram -- Intel 8259A Functional Equivalent Programmable Interrupt Controller
  • Intel 8259A Functional Equivalent Programmable Interrupt Controller
    • The DB8259S Programmable Interrupt Controller core is a full function equivalent to the Intel 8259A / Intersil 82C59A / NEC uPD8259A devices.
    • The DB8259S Interrupt Controller manages up to eight vectored priority interrupts for a microprocessor. Using multiple instantiations of the DB8259S core and programming it to cascade mode enables up to sixty-four vectored priority interrupts.
    • More than sixty four vectored interrupts can be accomplished by programming the DB8259S core to Poll Command Mode. Interrupt sources may be either edge or level triggered.
    Block Diagram -- Intel 8259A Functional Equivalent Programmable Interrupt Controller
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • Quad SPI Master IP
    • Compliant with AMBA AXI3/4 and AXI4-lite protocols.
    • User configurable clock frequency support
    • Designed to support all leading NOR FLASH devices.
    Block Diagram -- Quad SPI Master IP
  • xSPI Master IP | NOR IP
    • JESD 251 compliant
    • JEDEC SFDP Compliant
    Block Diagram -- xSPI Master IP | NOR IP
  • 8259A Interrupt Controller
    • Eight interrupt request input per chip
    • Up to 64 interrupt request inputs per system
    • Edge or level triggered interrupt request inputs
    • Individually maskable interrupt requestsProgrammable interrupt request priority orders
    Block Diagram -- 8259A Interrupt Controller
  • Parallel ATA IP Device Controller
    • Supports ATA protocol
    • Supports ATA-2 through ATA-6
    • Programmable I/O modes: 0, 1, 2, 3, and 4
    • Multi-word DMA modes: 0, 1, and 2
  • High Speed SPI AHB IP Core- Serial Peripheral Interface
    • High Speed SPI Interface
    • AHB Interface
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