ONFI IP

Welcome to the ultimate ONFI IP hub! Explore our vast directory of ONFI IP cores

The ONFI IP cores are used to access the external NAND flash for high speed transactions of multiple pages of read or write data taking advantage of the pipeline performance of newer enterprise NAND flash devices.

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Compare 68 ONFI IP from 20 vendors (1 - 10)
  • ONFI PHY & Controller
    • The ONFI IP provides Turnkey solutions for IC requiring access to ONFI-compatible NAND Flash devices
    • Optimized for low power and high-speed applications, it features robust timing and a compact silicon area
    • It supports all ONFI NAND Flash components available on the market
    Block Diagram -- ONFI PHY & Controller
  • NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
    • The NAND Flash Controller Verification IP (VIP) is a specialized tool for validating and simulating NAND Flash memory interfaces in System-on-Chip (SoC) designs. It ensures compliance with protocols, error correction, and optimal performance across varied conditions.
    • This versatile tool supports a wide range of applications, including automotive, consumer electronics, industrial automation, and aerospace. By guaranteeing reliable integration of NAND Flash memory, it enables seamless functionality in devices ranging from gaming consoles to mission-critical systems
    Block Diagram -- NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
  • Simulation VIP for ONFi
    • Speed
    • NV-DDR3: 800MHz, 1600MT/s (DDR)
    • NV-LPDDR4: 1200MHz, 2400MT/s (DDR)
    • Interfaces
    Block Diagram -- Simulation VIP for ONFi
  • Simulation VIP for OctaRam
    • Memory Size
    • 16Mb to 512Mb
    • SPI and Quad-SPI Mode
    • Quad Entry: Switch mode of operation from SPI to QSPI
    Block Diagram -- Simulation VIP for OctaRam
  • Simulation VIP for HyperRam
    • Density
    • From 64Mb to 128Mb
    • Reset
    • Hardware Reset via RESET# pin
    Block Diagram -- Simulation VIP for HyperRam
  • Simulation VIP for HyperFlash
    • Density
    • From 128Mb to 512Mb
    • General Functionality
    • Supports Status Register Read and Clear commands
    Block Diagram -- Simulation VIP for HyperFlash
  • Open Nand Flash Interface (ONFI)
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications.
    • Supports Source Synchronous and Asynchronous data interfaces.
    • Supports all mandatory and optional commands.
    • Supports 16 bit bus width operations.
    Block Diagram -- Open Nand Flash Interface (ONFI)
  • ONFI 5.0 Verification IP
    • Compliant to ONFI-2.3 ,ONFI-3.0 ,ONFI-4.0 ,ONFI-4.1 , ONFI-4.2 and ONFI-5.0 specifications.
    • Supports all mandatory and optional commands. Supports generation of Vendor Specific Commands.
    • Supports up to 16-bit bus width operations.
    • Supports implicit and explicit training (DCC, Read DQ, Write DQ Tx, Write DQ Rx).
    Block Diagram -- ONFI 5.0 Verification IP
  • NAND Flash Memory Controller with DMA
    • ONFI 4.0 support
    • BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
    • Randomization of memory data
    • Basic timeout based SEFI detection and reporting
    Block Diagram -- NAND Flash Memory Controller with DMA
  • ONFI 5.0 PHY
    • The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
    Block Diagram -- ONFI 5.0 PHY
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