Video Codec IP

Video codec IP cores encode and decode digital video signals in real-time. These cores are designed to offload the computationally intensive tasks of video compression and decompression from a general-purpose processor. By supporting various video standards such as H.264, HEVC, VP9, and AV1, video codec IP cores enable efficient video streaming, storage, and playback. They offer high performance, low power consumption, and flexibility, ensuring high-quality video experiences across a wide range of applications.

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Compare 379 Video Codec IP from 81 vendors (1 - 10)
  • Multi-format video decoder IP Core
    • Unified architecture supports multiple formats
    • VVC main profile 8/10bit
    • AV1 main profile 8/10bit
    • H.264 up to constraint high10 profile
    Block Diagram -- Multi-format video decoder IP Core
  • JPEG XS - Low-Latency Video
    • JPEG XS stands out with its extraordinary features. It delivers on low latency, ensuring real-time applications like video streaming and medical imaging run seamlessly.
    • Its high-quality compression preserves image fidelity, while progressive decoding allows for fast streaming. With a wide color gamut and support for resolutions up to 10K, JPEG XS redefines image compression, making it ideal for professional applications where image quality is non-negotiable.
    Block Diagram -- JPEG XS - Low-Latency Video
  • Video codec - AVC, MVC, MPEG-4, VC-1, MPEG-2, H.263, AVS Jizhun, AVS+ Guangdian, On2 VP8, Sorenson Spark, Theora
    • Supports up to 4K30fps
    • Multi-view Video Coding for Blu-ray 3D
    • Full coverage of stream on a web browser
    • Multi-level clock gating
    Block Diagram -- Video codec - AVC, MVC, MPEG-4, VC-1, MPEG-2, H.263, AVS Jizhun, AVS+ Guangdian, On2 VP8, Sorenson Spark, Theora
  • Video Scaler with Shrink and Zoom Support
    • The VSC-1 is a high quality polyphase scaler which has been optimized for video and graphics applications.
    • The scaler may be used in conjunction with the VPC-1 Video Processor and Deinterlacer IP core or with any other customer or third party IP.
    • Support for both shrink and zoom modes allows full screen display of any video or graphics source as well as arbitrary resizing for PIP applications. 
    Block Diagram -- Video Scaler with Shrink and Zoom Support
  • Video Processor and Deinterlacer with Line-Doubled Output
    • The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output.
    • Additional functions include motion adaptive noise reduction, low angle directional interpolation and film cadence detection (supports multiple cadences including 3:2, 2:2 and others).
    Block Diagram -- Video Processor and Deinterlacer with Line-Doubled Output
  • Configurable Multi-Viewer
    • The CMV-1 is a parameterized integration of the VSC-1 Scaler, VPC-1 Deinterlacer and other IP as required for multi-viewer applications.
    • The CMV-1 greatly simplifies the development of multi-viewer applications while allowing flexible system design through the use of Verilog build-time parameters.
    • For instance, the system may be configured to allow for up to 32 video sources and one or more display outputs. 
    Block Diagram -- Configurable Multi-Viewer
  • Scalable Ultra-High Throughput H.264 Encoder − Full Motion Estimation
    • The UHT-H264E-FME core is a scalable, ultra-high throughput, hardware H.264 encoder, designed to enable 4K and 8K Ultra HD resolutions in power- and cost-effective FPGA or ASIC implementations.
    • Powered by a highly-featured Full Motion Estimation engine, this encoder is the most advanced one of our UHT H.264 IP cores and offers best-in-class compression for applications needing advanced H.264 efficiency for high-quality, low-bitrate video encoding.
    Block Diagram -- Scalable Ultra-High Throughput H.264 Encoder − Full Motion Estimation
  • Scalable Ultra-High Throughput H.264 Encoder − Light Motion Estimation
    • The UHT-H264E-LME core implements a simple and flexible, requests based, external memory interface with independent read and write data paths.
    • The external memory I/F is also designed to be tolerant to memory delays and latencies, which may be present in a shared memory system architecture.
    Block Diagram -- Scalable Ultra-High Throughput H.264 Encoder − Light Motion Estimation
  • Scalable Ultra-High Throughput H.264 Encoder − Intra Frames (IDR) Encoding
    • The UHT-H264E-IDR core implements a simple and flexible, requests based, external memory interface with independent read and write data paths.
    • The external memory I/F is also designed to be tolerant to memory delays and latencies, which may be present in a shared memory system architecture.
    Block Diagram -- Scalable Ultra-High Throughput H.264 Encoder − Intra Frames (IDR) Encoding
  • High Profiles H.264 Encoder − High 10, High 4:2:2 and High 4:4:4 (12-bit 4:2:2 or 4:2:0) Profiles
    • The H264-HP-E core is an advanced and self-contained ITU-T H.264 High profiles hardware encoder.
    • This core is available in Intra-only [IDR], Light Motion Estimation [LME] and Full Motion Estimation [FME] prediction engine configurations.
    • It supports real time encoding of both single and multiple 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per component color depth, up to Profile Level 5.2. 
    Block Diagram -- High Profiles H.264 Encoder − High 10, High 4:2:2 and High 4:4:4 (12-bit 4:2:2 or 4:2:0) Profiles
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