Video Codec IP

The Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue.
The Color Enhancement can only adjust the color & brightness of the specific area that user wants. Therefore, no change in other regions due to color adjustment of each area.

The CMS0017 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 - Annexes A B and C. However, it does not include the Root-Raised-Cosine filters required by these standards.
The CMS0017 includes functions for framing, scrambling, interleaving, Reed-Solomon coding, trellis coding, and QAM mapping. With the exception of the common interleaver block, two independent datapaths are required.

The CMS0033 ATSC 8-VSB Modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
The core provides all the necessary processing steps to modulate a single transport stream into a complex I/Q signal for input to a pair of DACs, or a DDS up-conversion DAC such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.

The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
Simple, fully synchronous design with low gate count.

Fully compatible with the ITU-T H.264 baseline specification.
Proven in FPGA : VGA (640x480) at 30 fps in VirtexII-4 demo board.
Profile level 4.1, can be decoded by Main Profile decoder.
Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).

The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
Simple, fully synchronous design with low gate count.

Encoder fully compatible with the ITU-T H.264 specification.
Decoder limited to the subset produced by the encoder
Encoder proven in FPGA : VGA (640x480) at 30 fps or 720p @ 15 fps in Virtex4-10 demo board with video streamed to Ethernet.
Profile level 4.1, can be decoded by Baseline, Main or Hi Profile decoder.

The SMPTE292 core set, coupled with the AMCC S8401/S8501 serializer/deserializer chipset is fully compliant to the SMPTE 292M specification for Bit Serial Interfaces for High Definition Television Systems.
The core set includes separate Xilinx Virtex/Spartan-II cores for transmitter coding (scrambling and NRZI) and receiver decoding (NRZ, descrambling, sync detect and word framing)