IP Catalog > Multimedia IP > Video Codec IP

Video Codec IP

Video codec IP cores encode and decode digital video signals in real-time. These cores are designed to offload the computationally intensive tasks of video compression and decompression from a general-purpose processor. By supporting various video standards such as H.264, HEVC, VP9, and AV1, video codec IP cores enable efficient video streaming, storage, and playback. They offer high performance, low power consumption, and flexibility, ensuring high-quality video experiences across a wide range of applications.

All offers in Video Codec IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (348)
Compare 348 Video Codec IP from 74 vendors (1 - 10)
  • H.264 Decoder
    • Thes H.264 Decoder IP Core offers a high-efficiency video decoding solution tailored for a wide range of applications, including multimedia, surveillance, broadcast, and automotive systems.
    • Compliant with the ITU-T H.264/AVC standard, it enables real-time decoding of high-definition video streams while maintaining low latency and power consumption.
    Block Diagram -- H.264 Decoder
  • H.265 Decoder
    • The H.265 (HEVC – High Efficiency Video Coding) Decoder IP core delivers high-performance video decompression for next-generation visual applications, including broadcast, surveillance, automotive, and consumer electronics.
    • It supports real-time decoding of ultra-high-definition (UHD) video streams, up to 4K and 8K resolutions, while significantly reducing bandwidth and storage requirements without compromising video quality.
    Block Diagram -- H.265 Decoder
  • H.265 Encoder
    • The H.265 (HEVC – High Efficiency Video Coding) Encoder IP core enables efficient, high-quality video compression for applications requiring low bandwidth and high-resolution output, such as broadcasting, video conferencing, surveillance, automotive, and cloud-based video services.
    • It delivers real-time encoding of ultra-high-definition (UHD) content, significantly reducing storage and transmission demands while preserving visual fidelity.
    Block Diagram -- H.265 Encoder
  • H.264 Encoder
    • The H.264 Encoder IP Core delivers a high-performance video compression solution ideal for applications such as surveillance, broadcast, mobile, and automotive systems.
    • Fully compliant with the ITU-T H.264/AVC standard, it enables efficient encoding of video streams with excellent visual quality and reduced bandwidth requirements.
    Block Diagram -- H.264 Encoder
  • AV1 Video Encoder IP
    • ‘Pulsar-AV1’ is a fully hardwired AV1 video encoder IP that offers high computational and compression efficiency beyond customer-grade.
    Block Diagram -- AV1 Video Encoder IP
  • VMAF Video Quality Metric Accelerator IP
    • Fully hardwired IP
    • High performance
    • Supported Quality Metrics
    • Built-in Video Scaler
    Block Diagram -- VMAF Video Quality Metric Accelerator IP
  • Color Enhancement IP
    • The Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue.
    • The Color Enhancement can only adjust the color & brightness of the specific area that user wants. Therefore, no change in other regions due to color adjustment of each area.
    Block Diagram -- Color Enhancement IP
  • J.83abc/DVB-C Cable FEC Encoder
    • The CMS0017 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 - Annexes A B and C. However, it does not include the Root-Raised-Cosine filters required by these standards.
    • The CMS0017 includes functions for framing, scrambling, interleaving, Reed-Solomon coding, trellis coding, and QAM mapping. With the exception of the common interleaver block, two independent datapaths are required.
    Block Diagram -- J.83abc/DVB-C Cable FEC Encoder
  • ATSC 8-VSB modulator
    • The CMS0033 ATSC 8-VSB Modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
    • The core provides all the necessary processing steps to modulate a single transport stream into a complex I/Q signal for input to a pair of DACs, or a DDS up-conversion DAC such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.
    Block Diagram -- ATSC 8-VSB modulator
  • HDTV H.264/AVC Limited Baseline Video Decoder
    • The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
    • The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
    • Simple, fully synchronous design with low gate count.
    Block Diagram -- HDTV H.264/AVC Limited Baseline Video Decoder
×
Semiconductor IP