Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

All offers in Interface IP Cores
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 3,413 Interface IP Cores from 178 vendors (1 - 10)
  • eDisplayPort v1.4 Transmitter Controller IP Core
    • Supports eDP 1.4b specification
    • Supports full eDP Transmitter functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality
    Block Diagram -- eDisplayPort v1.4 Transmitter Controller IP Core
  • AXI Bridge with DMA for PCIe IP Core
    • The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
    • AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.
    Block Diagram -- AXI Bridge with DMA for PCIe IP Core
  • Multi-Channel AXI DMA Engine
    • The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
    • These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.
    Block Diagram -- Multi-Channel AXI DMA Engine
  • AXI Bridge for PCIe IP Core
    • The AXI Bridge for PCIe IP core is the  IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.
    • The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
    • All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.
    Block Diagram -- AXI Bridge for PCIe IP Core
  • 64G SerDes
    • 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
    • Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
    • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
    • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
    Block Diagram -- 64G SerDes
  • 112G SerDes USR & XSR
    • 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
    • Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
    • Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
    • Digitally-control-impedance termination resistors
    Block Diagram -- 112G SerDes USR & XSR
  • VDC-M 1.2 Encoder
    • VESA Display Compression-M (VDC-M) 1.2 Compliant
    • 8, 10, or 12 bits per Color Support
    • 4:4:4 RGB Native Encoding
    • 4:4:4, 4:2:2, or 4:2:0 YCbCr Native Encoding
    Block Diagram -- VDC-M 1.2 Encoder
  • VDC-M 1.2 Decoder
    • VESA Display Compression-M (VDC-M) 1.2 Compliant
    • Ultra-low Latency
    • Reduces Power and System Costs
    • Slice Configuration : 1, 2, 3, 4
    • Optimized for Power Saving
    Block Diagram -- VDC-M 1.2 Decoder
  • Ultra-Low-Latency 10GE PHY+MAC
    • Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit 
    • Reconciliation sub-layer implementation compliant with IEEE802.3 
    • Local fault and remote fault detection and handling 
    • Frame Check Sequence (FCS) insertion and verification at line rate 
    Block Diagram -- Ultra-Low-Latency 10GE PHY+MAC
  • Ultra Low Latency 10G TCP Endpoint
    • The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
    • It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.
    Block Diagram -- Ultra Low Latency 10G TCP Endpoint
×
Semiconductor IP