Interface IP Cores

The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K.
The core supports 8, 10, 12, 14 or 16 bits per pixel input using either RGB or YCbCr in 4:4:4 or 4:2:2 format.
The DSC Encoder core integrates industry standard interfaces for host configuration and control, video input, and output.

The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from 480 to 8K.
The core supports 8, 10, 12, 14 or 16 bits per pixel using either RGB or YCbCr in 4:4:4 or 4:2:2 format.
The DSC Decoder core integrates industry standard interfaces for host configuration and control, data input, and video output.

Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort 1.5.
Features include link rates up to 20Gbps for DisplayPort 2.0, 8.1Gbps for DisplayPort 1.4a. Display Steam Compression (DSC), multi-stream transport (MST) and more. The base core includes all required link functionality— Main Link, Secondary Channel, and AUX Channel protocols—and supports the HDCP 2.3 standards for data encryption.

Silicon proven on multiple ASIC and FPGA processes
Capable of operating without a host CPU in low complexity applications
Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes

The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
The core is compatible with the Philips I²C standard and supports 7- and 10-bit addressing with an optionally software programmable address.
Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
The I²C-master core is a modified version of the OpenCores I²C-Master where the WISHBONE interface has been replaced with an AMBA APB interface.
The core is compatible with Philips I²C standard and supports 7- and 10-bit addressing. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.

USB 2.0 High-Speed functionality is supplied by an enhanced host controller implementing the Enhanced Host Controller Interface (EHCI).
Full- and Low-Speed functionality (USB 2.0 and USB 1.1) is supplied by one or more companion controllers implementing the Universal Host Controller Interface (UHCI).
The Port Router supplies the dynamic connection between the host controllers and the USB transceivers.

The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
An external PHY compliant with either UTMI, UTMI+ or ULPI is needed to connect to the USB.

The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).
Data is transmitted and received through 9-bit wide FIFOs with configurable depth. The core also provides an interface for transmitting and receiving Time-codes as well as configuring the link properties such as the link rate.