IP Catalog > Interface IP Cores

Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

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Search (3,391)
Compare 3,391 Interface IP Cores from 173 vendors (1 - 10)
  • Verification IP for UALink
    • API based transaction flow for ease of use
    • Specification linked Protocol checks and functional coverage
    • Exceptions, callback, error injection and analysis ports for Scoreboard
    • TLM ports at each layer for traffic tracing 
    • Configurable timers for threshold testing
    Block Diagram -- Verification IP for UALink
  • CXL 4.0/3.2/3/2 Verification IP
    • Compliant with the CXL 3.2, 2.0 & 1.1 Specification.
    • Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
    • Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
    • Support for 256B flit in 64GT/s with PCIe Gen 6 as well as 32/16/8 GT/s speeds with backward compatibility.
    Block Diagram -- CXL 4.0/3.2/3/2 Verification IP
  • Ultra Ethernet Verification IP
    • The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
    • The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
    • This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
    Block Diagram -- Ultra Ethernet Verification IP
  • 100G MAC and PCS core
    • KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
    • The core implements RS FEC as defined in IEEE 802.3bj Clause 91 with independent bit error detection and bit error correction.
    Block Diagram -- 100G MAC and PCS core
  • 100G UDP/IP Hardware Protocol Stack Core
    • The core Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
    • It is ideal to offload systems from demanding tasks of UDP/IP and to enable media streaming in both FPGA and RISC designs.
    • The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included.
    Block Diagram -- 100G UDP/IP Hardware Protocol Stack Core
  • 40G MAC and PCS core
    • KMX 40G MAC and PCS core, which including media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
    • The core supports RS FEC as defined in Clause 74 IEEE 802.3 with independent error bit detection and error bit correction.
    Block Diagram -- 40G MAC and PCS core
  • Ethernet TSN MAC 40G/100G
    • Silicon agnostic Ethernet TSN MAC IP with speeds of 40G and 100G, based IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features
    Block Diagram -- Ethernet TSN MAC 40G/100G
  • I2C Slave Serial Interface Controller
    • The I2C_SLAVE IP Core is a Philips® I2C compliant slave interface controller.
    • The controller decodes the SCL and SDA bus signals and converts them into a simple series of 8-bit read/write commands for accessing a set of user-defined registers.
    • These registers are defined as either configuration registers or status registers.
    Block Diagram -- I2C Slave Serial Interface Controller
  • I2C Master Serial Interface Controller
    • The I2C_MASTER IP Core is a Philips® I2C compliant serial interface controller capable of driving a standard two-wire bus in single-master mode.
    • The controller receives data and instructions via the master instruction interface.
    • These instructions are then processed by the controller state-machine in order to generate the appropriate responses on the SCL and SDA lines.
    Block Diagram -- I2C Master Serial Interface Controller
  • High-Speed LVDS (SERDES) Transceiver
    • The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
    • The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.
    Block Diagram -- High-Speed LVDS (SERDES) Transceiver
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