Interface IP Cores

The 100G Ethernet Verification IP (VIP) offers a robust and high-performance solution for validating the critical MAC-to-PCS datapath in 100 Gigabit Ethernet systems.
Designed to ensure protocol compliance, the VIP facilitates the generation, transmission, reception, and monitoring of various Ethernet MAC frame types, all while adhering to IEEE 802.3ba and related standards.
Whether you are working on IP, subsystem, or SoC-level verification, this VIP is your go-to solution for comprehensive Ethernet testing.

The OTL Verification IP Product is the comprehensive OTL interface protocol validation solution.
ITU-T recommendation G.709 annexure C defines OTL interface mechanism by which OTU4 and OTU3 signals can be car ried for short-reach client side applications.
OTU4 signals can be carried over 10 parallel lanes, which are formed by bit multiplexing of 20 logical lanes. OTU3 signals can be car ried over 4 parallel lanes.

INTERLAKEN VIP is reusable, highly configu rable, pre-verified, plug-and-play verification component developed in System Verilog - UVM, which is solution for networking based SoC incorporating INTERLAKEN packet interface protocol at Module, Chip and System level.
INTERLAKEN VIP is developed using System Verilog, the unified language for Design & Verification and UVM reusable verification methodology.

UALink, the standard for AI accelerator interconnects, facilitates this scalability by providing low-latency, high-bandwidth communication.
As a member of the UALink Consortium, Cadence offers verified UALink IP subsystems, including controllers and silicon-proven PHYs, optimized for robust performance in both short and long-reach applications and delivering industry-leading power, performance, and area (PPA).

Compliant with the CXL 3.2, 2.0 & 1.1 Specification.
Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
Support for 256B flit in 64GT/s with PCIe Gen 6 as well as 32/16/8 GT/s speeds with backward compatibility.

The PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration.
Supporting PCIe Gen1 through Gen6 at data rates up to 64 GT/s, the controller accommodates a wide range of link widths (x1–x16) and protocol features to meet the demands of next-generation SoC, networking, and high-performance computing platforms.
The controller seamlessly interoperates with PIPE-compliant PHYs and supports multiple modes including Root Complex, Endpoint, Switch, and Dual-Mode operation.

Implements PCIe 6.0 Specification at 64 GT/s
Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
Designed for easy integration with Alphawave PipeCORE™ PCIe PHY IP
Key IP features configurable to optimize IP for exact application requirements

Fully compliant with HDMI 1.4 and 2.0 specifications
Supports High Bandwidth: Supports up to 18 Gbps (R, G, B), allowing for higher resolutions, faster refresh rates, and more color depth
Supports High Dynamic Range (HDR): Compatible with HDR formats, enhancing the contrast and color accuracy of the displayed content
Supports four (4) operation modes

The PCI Express specification allows endpoints that incorporate several physical PCIe functions that share the same PCIe connection. Such endpoints are called multi-function devices.
The big advantage of a multi-function device is, that a separate device driver can be associated to each physical function.
This simplifies driver development and maintenance significantly by separating the peripheral functions logically into different device drivers.