IP Catalog > Interface IP

Interface IP

Welcome to the ultimate Interface Protocol IP hub! Explore our vast directory of Interface Protocol IP such as Ethernet, USB, PCIe, DDR, HBM, CXL, HDMI, MIPI, Die-to-Die UCIe, and much more

Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs.

All offers in Interface IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (4,925)
Compare 4,925 Interface IP from 195 vendors (1 - 10)
  • PCIe 6.0 Retimer Controller with CXL Support
    • Designed to the latest PCI Express 6.0 (64 GT/s), and capable of supporting 32.0, 16.0, 8.0, 5.0 and 2.5 GT/s link rates
    • Supports x1, x2, x4, x8 and x16 link widths
    • CXL aware and supports sync header bypass
    • Supports PIPE 5.2/6.1 compatible PHYs
    • Optimized data-path for low latency insertion
    Block Diagram -- PCIe 6.0 Retimer Controller with CXL Support
  • PCIe 6.2 Switch
    • 1 upstream port, up to 7 downstream ports
    • Up to 128 lanes
    • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
    • L1 and wake-up events forwarding
    Block Diagram -- PCIe 6.2 Switch
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • PCIe 7.0 Switch
    • Configurable from PCIe 7.0 x8/ PCIe6x16 @1GHz clock down to PCIe 5.0 x1
    • Highly scalable with up to 31 configurable external or embedded endpoints
    • Configurable Egress Buffer for non-blocking output queueing switch performance
    • Flit mode to non-Flit mode conversion
    • Low power optimized
    • Superior performance through a nonblocking architecture
    • Minimized footprint
    Block Diagram -- PCIe 7.0 Switch
  • PCIe 7.0 Retimer Controller with CXL Support
    • Supports PCIe 7.0 128 GT/s speeds at up to x16 lanes
    • CXL 3.0 aware
    • Supports PIPE 6.2.1 compatible PHYs
    • Optimized for low latency
    • Highly-configurable equalization algorithms and adaptive behaviors
    Block Diagram -- PCIe 7.0 Retimer Controller with CXL Support
  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 Controller
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
    • Look-ahead activate, precharge, and auto-precharge logic
    • Parity protection for all stored control registers
    • PHY interface based on DFI 5.1 standard
    Block Diagram -- LPDDR5T / LPDDR5X / LPDDR5 Controller
  • Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable
    • Full wire-speed on all ports and all Ethernet frame sizes.
    • Store and forward shared memory architecture.
    • Support for jumbo packets up to 32739 bytes.
    Block Diagram -- Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable
  • GDDR7 Memory Controller
    • Supports up to 40 Gbps per pin operation
    • 2.5 GHz CK4 clock
    • 1.25 GHz controller clock
    • Internal data path 32x memory width (i.e. 256 bits for 8-bit memory)
    • Optimized for high efficiency and low latency across a wide range of traffic scenarios (random/sequential, short/long bursts, etc.)
    • Optimized command sequence for highest bus utilization including per-bank refresh scheduling: single queue structure handles look-ahead activates/ precharges and read/write ordering for minimal latency
    Block Diagram -- GDDR7 Memory Controller
×
Semiconductor IP