Interface IP Cores
Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.
Explore our vast directory of Interface IP cores below.
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Interface IP Cores
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Interface IP Cores
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Simulation VIP for MIPI CSI-2
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Generates constrained-random bus traffic with predefined error injection at CSI-2, D-PHY, C-PHY and A-PHY levels
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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Simulation VIP for MIPI M-PHY
- Specification Compliance
- Complies with MIPI M-PHY 4.0, 4.1 and 5.0 specification
- M-PHY Type 1 and Type 2
- Supports Type 1 and Type 2
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Simulation VIP for MIPI UniPro
- Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules
- Error detection: Supports error detection on all layers, more than 240 different protocol checks
- Coverage: Monitors, checks, and collects coverage on bus traffic using hundreds of automatic protocol checks, including configuration and runtime checks
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Simulation VIP for eUSB2V2
- The Verification IP (VIP) for eUSB2v2 is a complete VIP solution for the embedded USB2 (eUSB2) version 2.0.
- It provides a mature and comprehensive verification IP (VIP) for the eUSB2v2 protocol.
- Incorporating the latest protocol updates, the eUSB2v2 VIP is not only a complete bus functional model (BFM) for the eUSB2v2 DUT, but it also provides integrated automatic protocol checks and coverage models.
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Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
- Automotive Documentation including Safety Manual, FMEDA and DFMEA
- Design reliability report containing EM/IR and Aging analysis
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Simulation VIP for Ethernet UEC
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
- Transaction Tracker: Configurable tracking of all the transactions on the channels
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Simulation VIP for UALink
- The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a complete bus functional model (BFM) with integrated automatic protocol checks for physical layer in addition to Media Independent Interface (MII).
- Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
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MIPI SoundWire I3S Manager IP
- The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
- Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.
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MIPI SoundWire I3S Peripheral IP
- The MIPI SoundWire I3S Peripheral IP delivers seamless, low-power, and high-quality audio connectivity for a range of mobile, consumer, and automotive devices.
- Fully compliant with the MIPI SoundWire I3S (Inter-IC Sound) specifications, it enables synchronized, multi-channel audio communication with a compact and efficient two-wire interface, ideal for integrating digital microphones, amplifiers, or audio codecs.
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MIPI SoundWire I3S Verification IP
- Full MIPI SoundWire I3S Master, Slave and Monitor functionality
- Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
- Supports system with one master and one or more slaves (upto 8 slaves).
- Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
