Interface IP Cores

Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System can support short-reach or long-reach channels for plenty application scenarios.
Brite PCIe controller to AXI architecture provides a high-performance, easy-to-use interconnect solution between PCI Express and the latest version of the AXI protocol. It inherits the leading architecture and features an AXI user interface with built-in DMA, compliant with the AMBA® AXI3 and AXI4 specifications.

Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design.
The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 12Mbps protocol and data rates.
It has been verified by a number of end products, especially suitable for the current popular internet of things applications.

Brite provides full solution for the MIPI CSI interface, which receives the data from sensors in PHY layer, and then converts the byte data to pixel after lane data mergence.
Data scramble is an optional feature to decrease the EMI effect.
A standard PPI interface is implemented for the connection between MIPI PHY and CSI controller. Brite MIPI CSI interface solution supports image applications with varying pixel formats.

YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate good performance class performance, area and power.
The programmable PHY supports major standards such as PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, XAUI, SATA Gen 3.0/2.0/1.0, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.

Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.

Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications
Less than 4000 Xilinx slices, Altera ALMs or 150,000 ASIC gates + on-chip memory
Fully integrated 100 M bit/1-G bit high performance EMAC.
Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.

MIL-STD-1553B IP Core implements MIL-STD-1553B standard and provides single or multi-functional interface between host processor and MIL-STD-1553 bus transceiver.
DO-254 compliant MIL-STD-1553B IP core can function as Bus Controller (BC), two separate Remote Terminals (RT) and Bus Monitor (BM), simultaneously.

The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface.
It supports both USB Host and USB Device peripheral functionality.
While acting as USB Host, it supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.
While acting as USB Device peripheral, it supports High Speed (HS) and Full Speed (FS) modes.

Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.

I²S Controller is designed to transfer audio data to and from Audio codec.
It can be configured as both Master and Slave mode using software.
The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.