The Semiconductor IP Marketplace

Spotlight

• Secure Storage Solution for OTP IP

  • Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
  • System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
  • Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs
  
• UDP Offload Engine for IPv6

  • Full IPv6 support including Echo, NDP, MLD
  • Line-rate UDP/IPv6 transmit and receive
  • RFC 768 & RFC 8200 compliant
  • Packet parsing and header synthesis in hardware
• Public-Key Cryptography PKCS IP Core

  • Comprehensive implementation in accordance with RSA Laboratories' Public-Key Cryptography Standards (PKCS) series, PKCS #5 v2.0
  • Support for SHA256 algorithm
  • Technology-independent HDL model
  • Simple external interface for easy adaptation
• Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem

  • Ultra-low Power-Smallest, sleepiest LPDDR3 subsystem for real bandwidth & compatibility
  • Power-first architecture optimized for low-speed & small footprint, with multiple system-level power saving features.
  • Pin-compatible design enables seamless migration to next-gen devices and supports board-reuse.
• Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+

  • Ultra-Low Leakage: High VT (HVT) and low leakage (LLHVT) devices are used with source biasing to minimize standby currents while operating at low voltage 
  • Bit Cell: Utilizes GlobalFoundries®  Ultra-Low Leakage  6T (P110UL) bit cells to ensure high manufacturing yields 
  • Five Power Modes: High Performance, Low Leakage, Standby, Retention, and Power Off modes provide flexibility for power optimization 
  • Speed Grades: Three options to adjust the speed/leakage balance and optimize for high speed or low power operation 
  
• MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP

  • Technology is TSMC 22nm ULP 1p10M.
  • Supply voltage can be applied 1.0V for core voltage, 1.8V  for IO voltage.
  • Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
  • Data rate of each channel is 609Mbps for FPD-Link(LVDS).
  

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
  
• TSMC CLN5FF GUCIe LP Die-to-Die PHY

  • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
  • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
  

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Separate native TX/RX data path separating posted/Non posted/completion traffic
  • Handles up to 4 TLPs per cycle
  • Advanced PIPE modes and port bifurcation
  
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• RISC-V CPU IP

  • RISC-V RVA23 Compliant 
  • >18 SPECint2006/GHz
  • 8-wide decode unit
  • Advanced branch predictor
  
• NPU IP for Embedded ML

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
  
• Future-proof IP for training and inference with leading performance per watt and per dollar

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.
  

MIPI IP View All

• MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

  • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
  • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
  
• MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
• MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

  • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  
• High-performance RISC-V CPU

  • Fully compliant with the RVA23 RISC-V specification
  • Comparable PPA to Arm Neoverse V3 / Cortex-X4
  • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
  • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations