The Semiconductor IP Marketplace

Try an example: PCIe 7.0
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The Semiconductor IP Marketplace that puts you first

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Spotlight

  • Complex Digital Up Converter
    • High-precision 16-bit complex digital up-converter / IQ modulator (DUC) with a fully configurable interpolation filter stage.
    • Ideal for the conversion of baseband signals to IF.
    • Features a precision digital oscillator (DDS) and an optimized interpolation filter section.
       
  • Bluetooth Low Energy 6.0 Digital IP
    • The SB1001-CM BLE 6.0 digital modem and baseband controller IP enables industry-leading, ultra-efficient, wireless SoCs for multiple connected applications.
    • Industry leading modem link budget for RF environment reliability and resilience, industry leading support for scalable numbers of connections and a Zephyr driver for ease of host integration
  • Verification IP for Ultra Ethernet (UEC)
    • Native SystemVerilog/UVM
    • Source code test suite including UNH-IOL (optional)
    • Runs natively on major simulators
    • Built-in protocol checks
    • Verification plan and coverage
    Block Diagram -- Verification IP for Ultra Ethernet (UEC)
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • Ultra-low power high dynamic range image sensor
    • Resolution: VGA (640 x 480)
    • Backside illuminated sensor
    • Pixel size: 6.3 μm x 6.3 μm
    • Fill factor: 83 %
    • Dynamic range: 120 dB intra-scene
    Block Diagram -- Ultra-low power high dynamic range image sensor
  • Neural Video Processor IP
    • The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the advanced features and benefits of AI based video processing technologies.
    • The NVP300 IP features an optimized hardware implementation to deliver real-time AI processing of 4K video whithin best-in-class silicon area and power budget suitable for embedded products.

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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