The Semiconductor IP Marketplace

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Spotlight

  • Ultra-Secure, PQC-first, Root-of-Trust Security Platform
    • A complete PQC-focused security system that provides architects with the tools needed for the quantum age and beyond.
    • PQPlatform-TrustSys is a fully programmable Root-of-Trust subsystem, containing advanced post-quantum (ML-KEM, ML-DSA) and classical cryptography (ECC and RSA – essential for hybrid and legacy protocols during transition), enabling bulk encryption, hash acceleration, advanced accelerators for symmetric cryptography, including AES, SHA2, SHA3, HMAC, and seamless integration with third-party components.
    • PQPlatform-TrustSys can also be deployed with our world-leading fault-tolerance and power/EM side-channel attack countermeasures.
    Block Diagram -- Ultra-Secure, PQC-first, Root-of-Trust Security Platform
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 5G IoT DSP
    • The XC21 is the most efficient vector DSP core available today for communications applications.
    • The XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications.
    • Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices
    Block Diagram -- 5G IoT DSP
  • PCIe GEN6 PHY IP
    • The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
    • It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
    Block Diagram -- PCIe GEN6 PHY IP
  • PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication
    • The DPSI5 is a hardware implementation of a controller for the Peripheral Sensor Interface (PSI5) protocol. This controller complies with the PSI5 protocol specification V2.3 and is designed for use in electronic control units (ECUs) to ensure communication with up to six sensors.
    • Data transmission from the sensor to the ECU is achieved through current modulation on the power supply line, with a data rate of 125 kbit/s or 189 kbit/s, using a Manchester decoder.
  • Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module
    • The automotive-grade CryptoManager RT-7xx v3 Root of Trust family is the next generation of fully programmable ISO 26262 and ISO 21434 compliant hardware security modules offering Quantum Safe security by design for secure automotive applications.
    • The CryptoManager RT-7xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.
    Block Diagram -- Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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