Semiconductor IP Articles Archive - Page 3 of 227

Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory

By Guan-Cheng Chen, National Cheng Kung University

January 6, 2026

ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update

By Zhe Su, University of Zurich and ETH Zurich

December 26, 2025

A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

By Darja Nonaca, ETH Zurich

December 22, 2025

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

By Mostafa Darvishi, ÉTS, Montreal

December 17, 2025

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

By Juncheng Huo, Chinese Academy of Sciences

December 16, 2025

Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval

By Grant Bosworth, Rochester Institute of Technology

December 15, 2025

Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension

By Songqiao Cui, KU Leuven

December 10, 2025

ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes

By Dilli Babu Porlapothula, International Institute of Information Technology

December 9, 2025

In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

By Sanwar Ahmed Ovy, North Dakota State University

December 8, 2025

David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?

By Shashwat Shankar, Indian Institute of Technology

December 5, 2025

RoMe: Row Granularity Access Memory System for Large Language Models

By Hwayong Nam, Seoul National University

December 3, 2025

Analog Foundation Models

By Julian Büchel, IBM Research

December 2, 2025

Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators

By Jason Yik, Harvard University

December 1, 2025

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

By Muhammed Yildirim, Ihsan Dogramaci Bilkent University

November 28, 2025

Exclude Smart in Functional Coverage

By Shailesh Vasekar, Neurotech Circuits

November 27, 2025

A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

By Jonas Elmiger, ETH Zurich

November 27, 2025

Towards a Formal Verification of Secure Vehicle Software Updates

By Martin Slind Hagen, Chalmers University of Technology

November 25, 2025

Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training

By Yipeng Wang, University of Texas

November 24, 2025

Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security

By Saumitra Jagdale, Open Cloudware

November 24, 2025

SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration

By Arya Parameshwara, PES University

November 20, 2025