A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
April 10, 2025
Semiconductor IP Articles
Learning Cache Coherence Traffic for NoC Routing Design
April 9, 2025
Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
April 9, 2025
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction
April 9, 2025
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
April 8, 2025
A Time for Rebalancing Global Patent Strategies in the Semiconductor Market?
April 7, 2025
Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
April 4, 2025
The pivotal role power management IP plays in chip design
April 2, 2025
What tamper detection IP brings to SoC designs
April 1, 2025
Analyzing Modern NVIDIA GPU cores
March 31, 2025
RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
March 28, 2025
Leveraging RISC-V as a Unified, Heterogeneous Platform for Next-Gen AI Chips
March 27, 2025
Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
March 26, 2025
CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon
March 20, 2025
How AI is changing the game for high-performance SoC designs
March 10, 2025
A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
March 7, 2025
Adaptable Hardware with Unlimited Flexibility for ASIC & SoC ICs
March 6, 2025
CAST Provides a Functional Safety RISC-V Processor IP for Microchip FPGAs
March 4, 2025
Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
March 4, 2025
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk
March 3, 2025
