Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
By Juncheng Huo 1,2, Yunfan Gao 1,2, Xinxin Liu 3,4, Sa Wang 1,2, Yungang Bao 1,2, Xitong Gao 3,5 and Kan Shi 1,2
1 SKLP, Institute of Computing Technology, Chinese Academy of Sciences
2 University of Chinese Academy of Sciences
3 Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
4 Southern University of Science and Technology
5 Shenzhen University of Advanced Technology
Abstract
As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to 1.27× higher coverage and accelerates end-to-end verification by up to 107× to 3343× compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.
Keywords: Verification, RISC-V, LLM, FPGA
To read the full article, click here
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related Articles
- Efficient Verification of RISC-V processors
- A closer look at security verification for RISC-V processors
- Maven Silicon's RISC-V Processor IP Verification Flow
- A formal-based approach for efficient RISC-V processor verification
Latest Articles
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
- In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss