Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

By Juncheng Huo ^1,2, Yunfan Gao ^1,2, Xinxin Liu ^3,4, Sa Wang ^1,2, Yungang Bao ^1,2, Xitong Gao ^3,5 and Kan Shi ^1,2
1 SKLP, Institute of Computing Technology, Chinese Academy of Sciences
² University of Chinese Academy of Sciences
³ Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
⁴ Southern University of Science and Technology
⁵ Shenzhen University of Advanced Technology

Abstract

As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to 1.27× higher coverage and accelerates end-to-end verification by up to 107× to 3343× compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.

Keywords: Verification, RISC-V, LLM, FPGA

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