All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices
June 23, 2025
Semiconductor IP Articles
From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
June 17, 2025
QiMeng: Fully Automated Hardware and Software Design for Processor Chip
June 13, 2025
RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
June 13, 2025
Concealable physical unclonable functions using vertical NAND flash memory
June 11, 2025
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
June 9, 2025
Transition Fixes in 3nm Multi-Voltage SoC Design
June 8, 2025
CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
June 8, 2025
Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
June 4, 2025
Automating NoC Design to Tackle Rising SoC Complexity
June 4, 2025
Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor
June 3, 2025
Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
June 2, 2025
CSR Management: Life Beyond Spreadsheets
May 29, 2025
One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
May 28, 2025
Get More Reliable Automotive ICs with a Shift Left Design Approach
May 27, 2025
Evaluating Lossless Data Compression Algorithms and Cores
May 27, 2025
How to design secure SoCs, Part III: Secure Boot
May 26, 2025
Key Safety Design Overview in AI-driven Autonomous Vehicles
May 26, 2025
ACE: Confidential Computing for Embedded RISC-V Systems
May 22, 2025
Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
May 21, 2025
