Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
By Grant Bosworth 1, Keewoo Lee 2, and Sunwoong Kim 1
1 Rochester Institute of Technology, Rochester, NY, USA,
2 Ethereum Foundation
Abstract
While end-to-end encryption protects the content of messages, it does not secure metadata, which exposes sender and receiver information through traffic analysis. A plausible approach to protecting this metadata is to have senders post encrypted messages on a public bulletin board and receivers scan it for relevant messages. Oblivious message retrieval (OMR) leverages homomorphic encryption (HE) to improve user expe rience in this solution by delegating the scan to a resource-rich server while preserving privacy. A key process in OMR is the homomorphic detection of pertinent messages for the receiver from the bulletin board. It relies on a specialized matrix-vector multiplication algorithm, which involves extensive multiplications between ciphertext vectors and plaintext matrices, as well as homomorphic rotations. The computationally intensive nature of this process limits the practicality of OMR. To address this challenge, this paper proposes a hardware architecture to accelerate the matrix-vector multiplication algorithm. The building homomorphic operators in this algorithm are implemented using high-level synthesis, with design parameters for different parallelism levels. These operators are then deployed on a field programmable gate array platform using an efficient design space exploration strategy to accelerate homomorphic matrix vector multiplication. Compared to a software implementation, the proposed hardware accelerator achieves a 13.86x speedup.
Index Terms — Design space exploration, field-programmable gate array, high-level synthesis, homomorphic encryption, obliv ious message retrieval
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Leveraging ASIC AI Chips for Homomorphic Encryption
- The Future of Embedded FPGAs - eFPGA: The Proof is in the Tape Out
- Where automotive FPGAs stand in smart car designs
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks