AI in VLSI Physical Design: Opportunities and Challenges
October 14, 2025
Semiconductor IP Articles Archive - Page 5 of 227
cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications
October 8, 2025
From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs
October 8, 2025
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
October 6, 2025
A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
October 6, 2025
Runtime Energy Monitoring for RISC-V Soft-Cores
October 2, 2025
Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
September 30, 2025
eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
September 24, 2025
aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
September 18, 2025
Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
September 16, 2025
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems
September 16, 2025
CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
September 13, 2025
On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
September 10, 2025
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
September 5, 2025
Balancing Power and Performance With Task Dependencies in Multi-Core Systems
September 5, 2025
LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
September 5, 2025
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
September 2, 2025
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
September 1, 2025
Redefining Speed: How FPGAs are shaping the future of high-frequency trading
August 26, 2025
Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
August 25, 2025
