Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
January 19, 2025
Semiconductor IP Articles
Reimagining AI Infrastructure: The Power of Converged Back-end Networks
January 15, 2025
40G UCIe IP Advantages for AI Applications
January 13, 2025
Recent progress in spin-orbit torque magnetic random-access memory
January 13, 2025
What is JESD204C? A quick glance at the standard
January 9, 2025
Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
January 9, 2025
The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
January 8, 2025
Tackling Network-on-Chip (NoC) Scaling Challenges with a System-technology Co-optimization Approach
January 7, 2025
Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
January 6, 2025
Optimized Clocking Solutions for High-Performance Die-to-Die Interfaces
January 6, 2025
The backpropagation algorithm implemented on spiking neuromorphic hardware
December 18, 2024
The Benefits of a Multi-Protocol PMA
December 16, 2024
Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
December 16, 2024
eUSB2V2 with 4.8Gbps and Use Cases: A Comprehensive Overview
December 10, 2024
Bringing SOT-MRAM Tech Closer to Cache Memory
December 10, 2024
Early Interactive Short Isolation for Faster SoC Verification
December 6, 2024
Scaling AI Chip Design With NoC Soft Tiling
December 6, 2024
Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
December 4, 2024
Mathematical Certainty in Data Security
December 3, 2024
Pie: Pooling CPU Memory for LLM Inference
December 2, 2024