Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
December 1, 2025
Semiconductor IP Articles
RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
November 28, 2025
Exclude Smart in Functional Coverage
November 27, 2025
A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection
November 27, 2025
Towards a Formal Verification of Secure Vehicle Software Updates
November 25, 2025
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
November 24, 2025
Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security
November 24, 2025
SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
November 20, 2025
Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing
November 19, 2025
Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting
November 18, 2025
FengHuang: Next-Generation Memory Orchestration for AI Inferencing
November 17, 2025
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
November 14, 2025
FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
November 11, 2025
MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
November 10, 2025
AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
November 6, 2025
FeNN-DMA: A RISC-V SoC for SNN acceleration
November 4, 2025
Multimodal Chip Physical Design Engineer Assistant
November 3, 2025
An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software
November 3, 2025
Attack on a PUF-based Secure Binary Neural Network
October 29, 2025
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
October 28, 2025