CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
September 13, 2025
Semiconductor IP Articles
On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
September 10, 2025
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
September 5, 2025
Balancing Power and Performance With Task Dependencies in Multi-Core Systems
September 5, 2025
LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
September 5, 2025
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
September 2, 2025
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
September 1, 2025
Redefining Speed: How FPGAs are shaping the future of high-frequency trading
August 26, 2025
Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
August 25, 2025
Akida Exploits Sparsity For Low Power in Neural Networks
August 21, 2025
A new era of chip-level DRC debug: Fast, scalable and AI-driven
August 20, 2025
Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
August 20, 2025
Ultra Ethernet's Design Principles and Architectural Innovations
August 20, 2025
Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
August 20, 2025
ReGate: Enabling Power Gating in Neural Processing Units
August 19, 2025
Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML
August 18, 2025
RISC-V basics: The truth about custom extensions
August 15, 2025
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
August 14, 2025
Bridging Design Verification Gaps with Formal Verification
August 13, 2025
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
August 13, 2025
