TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link By Yichao Zhang, ETH Zurich March 3, 2026
AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance By Seungkwan Kang, KAIST February 27, 2026
LUTstructions: Self-loading FPGA-based Reconfigurable Instructions By Philippos Papaphilippou, University of Southampton February 25, 2026
CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval By Xinzhao Li, Villanova University February 24, 2026
GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon By Arya Tschand, Harvard University February 23, 2026
Creating a Frequency Plan for a System using a PLL By Julian Jenkins, Perceptia Devices February 18, 2026
RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs By Fabian Thomas, CISPA Helmholtz Center for Information Security Saarbrücken February 18, 2026
MING: An Automated CNN-to-Edge MLIR HLS framework By Jiahong Bi, Technische Universitat Dresden February 16, 2026
Fault Tolerant Design of IGZO-based Binary Search ADCs By Paula Carolina Lozano Duarte, Karlsruhe Institute of Technology February 13, 2026
A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access By Xiaoling Yi, MICAS-ESAT, KU Leuven February 13, 2026
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design By Yuchao Liao, University of Arizona February 12, 2026
IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology By Rasheed Kibria, University of Florida February 11, 2026
System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check By Luis Cunha, Universidade do Minho February 10, 2026
CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions By Simone Manoni, University of Bologna February 10, 2026
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security By Anh Kiet Pham, Nara Institute of Science and Technology February 5, 2026
In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning By Tommaso Spagnolo, Politecnico di Milano February 4, 2026
QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design By Nilesh Prasad Pandey, University of California San Diego February 2, 2026
ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design By Zhongkai Yu, University of California San Diego February 2, 2026
COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events By Mahmudul Hasan, University of Kansas January 30, 2026