A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
December 22, 2025
Semiconductor IP Articles
Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
December 17, 2025
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
December 16, 2025
Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
December 15, 2025
Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
December 10, 2025
ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
December 9, 2025
In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
December 8, 2025
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
December 5, 2025
RoMe: Row Granularity Access Memory System for Large Language Models
December 3, 2025
Analog Foundation Models
December 2, 2025
Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
December 1, 2025
RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
November 28, 2025
Exclude Smart in Functional Coverage
November 27, 2025
A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection
November 27, 2025
Towards a Formal Verification of Secure Vehicle Software Updates
November 25, 2025
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
November 24, 2025
Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security
November 24, 2025
SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
November 20, 2025
Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing
November 19, 2025
Pushing the Memory Bandwidth Wall with CXL-enabled Idle I/O Bandwidth Harvesting
November 18, 2025
