Attack on a PUF-based Secure Binary Neural Network
October 29, 2025
Semiconductor IP Articles
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
October 28, 2025
FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics
October 28, 2025
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
October 27, 2025
SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
October 23, 2025
DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
October 22, 2025
ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
October 21, 2025
Practical Considerations of LDPC Decoder Design in Communications Systems
October 15, 2025
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
October 15, 2025
A logically correct SoC design isn’t an optimized design
October 15, 2025
AI in VLSI Physical Design: Opportunities and Challenges
October 14, 2025
cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications
October 8, 2025
From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs
October 8, 2025
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
October 6, 2025
A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
October 6, 2025
Runtime Energy Monitoring for RISC-V Soft-Cores
October 2, 2025
Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
September 30, 2025
eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
September 24, 2025
aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
September 18, 2025
Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
September 16, 2025
