Akida Exploits Sparsity For Low Power in Neural Networks
August 21, 2025
Semiconductor IP Articles
A new era of chip-level DRC debug: Fast, scalable and AI-driven
August 20, 2025
Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
August 20, 2025
Ultra Ethernet's Design Principles and Architectural Innovations
August 20, 2025
Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
August 20, 2025
ReGate: Enabling Power Gating in Neural Processing Units
August 19, 2025
Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML
August 18, 2025
RISC-V basics: The truth about custom extensions
August 15, 2025
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
August 14, 2025
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
August 13, 2025
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
August 12, 2025
Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
August 5, 2025
CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
August 4, 2025
How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
July 24, 2025
Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
July 23, 2025
Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
July 22, 2025
How Mature-Technology ASICs Can Give You the Edge
July 21, 2025
Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY
July 17, 2025
How to design secure SoCs, Part V: Data Protection and Encryption
July 16, 2025
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
July 15, 2025
