Semiconductor IP Articles

An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

By Mohammad Javad Sekonji, Shahid Bahonar University of Kerman

March 23, 2026

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

By Jie Lei, Universitat Politècnica de València

March 20, 2026

A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

By Junyi Liu, University of Maryland

March 18, 2026

SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

By Kanishka Gunawardana, University of Peradeniya

March 13, 2026

An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS

By Qiyue Chen, University of Science and Technology of China

March 12, 2026

A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA

By Neelesh Gupta, University of Southern California

March 11, 2026

VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration

By Max Wipfli, ETH Zurich

March 9, 2026

PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability

By Ning Lyu

March 4, 2026

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link

By Yichao Zhang, ETH Zurich

March 3, 2026

AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance

By Seungkwan Kang, KAIST

February 27, 2026

LUTstructions: Self-loading FPGA-based Reconfigurable Instructions

By Philippos Papaphilippou, University of Southampton

February 25, 2026

CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval

By Xinzhao Li, Villanova University

February 24, 2026

GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon

By Arya Tschand, Harvard University

February 23, 2026

Creating a Frequency Plan for a System using a PLL

By Julian Jenkins, Perceptia Devices

February 18, 2026

RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs

By Fabian Thomas, CISPA Helmholtz Center for Information Security Saarbrücken

February 18, 2026

MING: An Automated CNN-to-Edge MLIR HLS framework

By Jiahong Bi, Technische Universitat Dresden

February 16, 2026

Fault Tolerant Design of IGZO-based Binary Search ADCs

By Paula Carolina Lozano Duarte, Karlsruhe Institute of Technology

February 13, 2026

A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access

By Xiaoling Yi, MICAS-ESAT, KU Leuven

February 13, 2026

Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design

By Yuchao Liao, University of Arizona

February 12, 2026

IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology

By Rasheed Kibria, University of Florida

February 11, 2026